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| Freescale Semiconductor Technical Data DSP56374 Rev. 1, 11/2004 Overview The DSP56374 is a high density CMOS device with 3.3 V inputs and outputs. NOTE This document contains information on a new product. Specifications and information herein are subject to change without notice. Finalized specifications may be published after further characterization and device qualifications are completed. The DSP56374 supports digital audio applications requiring sound field processing, acoustic equalization, and other digital audio algorithms. The DSP56374 uses the high performance, single-clock-per-cycle DSP56300 core family of programmable CMOS digital signal processors (DSPs) combined with the audio signal processing capability of the Freescale Semiconductor, Inc. (formerly Motorola) SymphonyTM DSP family, as shown in Figure 1. Significant architectural enhancements include a barrel shifter, 24-bit addressing, and direct memory access (DMA). The DSP56374 offers 150 million instructions per second (MIPS) using an internal 150 MHz clock. Table of Contents Section Page 1 Features........................................ 2 2 Documentation.............................. 4 3 Signal Groupings .......................... 4 4 Maximum Ratings ....................... 24 5 Power Requirements................... 25 6 Thermal Characteristics.............. 26 7 DC Electrical Characteristics ...... 26 8 AC Electrical Characteristics....... 27 9 Internal Clocks ............................ 27 10 External Clock Operation .......... 29 11 Reset, Stop, Mode Select, and Interrupt Timing ........................... 30 12 Serial Host Interface SPI Protocol Timing.......................................... 34 13 Serial Host Interface (SHI) I2C Protocol Timing ........................... 40 14 Programming the Serial Clock .. 42 15 Enhanced Serial Audio Interface Timing.......................................... 43 16 Timer Timing ............................. 48 17 GPIO Timing ............................. 48 18 JTAG Timing ............................. 50 19 Watchdog Timer Timing ............ 52 Appendix A Package Information. 53 Appendix B IBIS Model ................. 63 Data Sheet Conventions This data sheet uses the following conventions: OVERBAR "asserted" Used to indicate a signal that is active when pulled low (For example, the RESET pin is active when low.) Means that a high true (active high) signal is high or that a low true (active low) signal is low "deasserted" Means that a high true (active high) signal is low or that a low true (active low) signal is high Examples: Signal/ Symbol PIN PIN PIN PIN Logic State True False True False Signal State Asserted Deasserted Asserted Deasserted Voltage* VIL / VOL VIH / VOH VIH / VOH VIL / VOL Note: *Values for VIL, VOL, VIH, and VOH are defined by individual product specifications. (c) Freescale Semiconductor, Inc., 2004. All rights reserved. PRELIMINARY Features 5 15* 12 12* 3 Memory Expansion Area SHI Interface GPIO ESAI Interface ESAI_1 Interface Triple Timer Watch dog Timer Program RAM 6k x 24 ROM 20k x 24 X Data RAM 6k x 24 ROM 4k x 24 XM_EB Y Data RAM 6k x 24 ROM 4k x 24 YM_EB PIO_EB PM_EB DDB YDB XDB PDB GDB Peripheral Expansion Area Address Generation Unit Six Channel DMA Unit YAB XAB PAB DAB 24-Bit Bootstrap ROM DSP56300 Core Internal Data Bus Switch Clock Gen. Power Mgmt. PLL Program Interrupt Controller Program Decode Controller Program Address Generator Data ALU 24 x 24+5656-bit MAC Two 56-bit Accumulators 56-bit Barrel Shifter 4 JTAG OnCE XTAL EXTAL RESET PINIT/NMI MODA/IRQA/GPIO MODB/IRQB/GPIO MODC/IRQC/GPIO MODD/IRQD/GPIO * ESAI_1 and dedicated GPIO pins are not available in the 52-pin package. Figure 1. DSP56374 Block Diagram 1 1.1 * * * * * * * * * * 2 Features DSP56300 Modular Chassis 150 Million Instructions Per Second (MIPS) with a 150 MHz clock at an internal logic supply (QVDDL) of 1.25 V. Object Code Compatible with the 56K core. Data ALU with a 24 x 24 bit multiplier-accumulator and a 56-bit barrel shifter;16 bit arithmatic support. Program Control with position independent code support. Six-channel DMA controller. Provides a wide range of frequency multiplications (1 to 255), predivider factors (1 to 31), PLL feedback multiplier (2 or 4), Output divide factor (1, 2 or 4) and a power-saving clock divider (2i: i = 0 to 7) to reduce clock noise Internal address tracing support and OnCE for Hardware/Software debugging. JTAG port, supporting boundary scan, compliant to IEEE 1149.1. Very low-power CMOS design, fully static design with operating frequencies down to DC. STOP and WAIT low-power standby modes. PRELIMINARY Freescale Semiconductor Features 1.2 * * * * * On-chip Memory Configuration 6Kx24 Bit Y-Data RAM and 4Kx24 Bit Y-Data ROM. 6Kx24 Bit X-Data RAM and 4Kx24 Bit X-Data ROM. 20Kx24 Bit Program and Bootstrap ROM including a PROM patching mechanism. 6Kx24 Bit Program RAM. Various memory switches are available. See memory table below. Table 1. DSP56374 Memory Switch Configurations Bit Settings MSW1 X 0 0 1 1 MSW0 X 0 1 0 1 MS 0 1 1 1 1 Prog RAM 6K 2K 4K 8K 10K Memory Sizes (24-bit words) X Data RAM 6K 10K 8K 4K 4K Y Data RAM 6K 6K 6K 6K 4K Prog ROM 20K 20K 20K 20K 20K X Data ROM 4K 4K 4K 4K 4K Y Data ROM 4K 4K 4K 4K 4K 1.3 * * * * * * Peripheral modules Enhanced Serial Audio Interface (ESAI): up to 4 receiver pins and up to 6 transmitter pins, master or slave. I2S, Sony, AC97, network and other programmable protocols. Enhanced Serial Audio Interface I (ESAI_1): up to 4 receiver pins and up to 6 transmitter pins, master or slave. I2S, Sony, AC97, network and other programmable protocols. Note: Available in the 80 pin package only Serial Host Interface (SHI): SPI and I2C protocols, 10-word receive FIFO, support for 8, 16 and 24-bit words. Three noise reduction filter modes. Triple Timer module (TEC). Most pins of unused peripherals may be programmed as GPIO pins. Up to 47 pins can be configured as GPIO on the 80 pin package and 20 pins on the 52 pin package. Hardware Watchdog Timer 1.4 * Packages 80-pin and 52-pin plastic LQFP packages. Freescale Semiconductor PRELIMINARY 3 Documentation 2 Documentation Table 2 lists the documents that provide a complete description of the DSP56374 and are required to design properly with the part. Documentation is available from a local Freescale Semiconductor, Inc. (formerly Motorola) distributor, semiconductor sales office, Literature Distribution Center, or through the Freescale DSP home page on the Internet (the source for the latest information). Table 2. DSP56374 Documentation Document Name DSP56300 Family Manual DSP56374 User's Manual DSP56374 Technical Data Sheet DSP56374 Product Brief Description Detailed description of the 56300-family architecture and the 24-bit core processor and instruction set Detailed description of memory, peripherals, and interfaces Electrical and timing specifications; pin and package descriptions Brief description of the chip Order Number DSP56300FM/AD DSP56374UM/D DSP56374 DSP56374PB/D 3 Signal Groupings The input and output signals of the DSP56374 are organized into functional groups, which are listed in Table 3.. The DSP56374 is operated from a 1.25 V and 3.3 V supply; however, some of the inputs can tolerate 5.0 V. A special notice for this feature is added to the signal descriptions of those inputs. Table 3. DSP56374 Functional Signal Groupings Functional Group Power (VDD) Ground (GND) Scan Pins Clock and PLL Interrupt and mode control SHI ESAI ESAI_1 Dedicated GPIO Timer JTAG/OnCE Port Note: 1. 2. 3. 4. 5. Number of Signals1 11 9 1 3 Port H2 Port H2 5 5 12 12 15 3 4 Detailed Description Table 15. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Port C4 Port E5 Port G3 Pins are not 5 V. tolerant unless noted. Port H signals are the GPIO port signals which are multiplexed with the MOD and HREQ signals. Port G signals are the dedicated GPIO port signals. Port C signals are the GPIO port signals which are multiplexed with the ESAI signals. Port E signals are the GPIO port signals which are multiplexed with the ESAI_1 signals. 4 PRELIMINARY Freescale Semiconductor Signal Groupings 3.1 Power Table 4. Power Inputs Power Name PLLA_VDD (1) Description PLL Power-- The voltage (3.3 V) should be well-regulated and the input should be provided with an extremely low impedance path to the 3.3 VDD power rail. The user must provide adequate external decoupling capacitors between PLLA_VDD and PLLA_GND. PLLA_VDD requires a filter as shown in Figure 21 and Figure 22 below. See the DSP56374 technical data sheet for additional details. PLL Power-- The voltage (3.3 V) should be well-regulated and the input should be provided with an extremely low impedance path to the 3.3 VDD power rail. The user must provide adequate external decoupling capacitors between PLLP_VDD and PLLP_GND. PLL Power-- The voltage (1.25 V) should be well-regulated and the input should be provided with an extremely low impedance path to the 1.25 VDD power rail. The user must provide adequate external decoupling capacitors between PLLD_VDD and PLLD_GND. Core Power--The voltage (1.25 V) should be well-regulated and the input should be provided with an extremely low impedance path to the 1.25 VDD power rail. The user must provide adequate external decoupling capacitors. SHI, ESAI, ESAI_1, WDT and Timer I/O Power --The voltage (3.3 V) should be well-regulated, and the input should be provided with an extremely low impedance path to the 3.3 VDD power rail. This is an isolated power for the SHI, ESAI, ESAI_1, WDT and Timer I/O. The user must provide adequate external decoupling capacitors. PLLP_VDD(1) PLLD_VDD (1) CORE_VDD (4) IO_VDD (80-pin 4) (52-pin 3) 3.2 Ground Table 5. Grounds Ground Name PLLA_GND(1) Description PLL Ground--The PLL ground should be provided with an extremely low-impedance path to ground. This connection must be tied externally to all other chip ground connections. The user must provide adequate external decoupling capacitors between PLLA_VDD and PLLA_GND. PLL Ground--The PLL ground should be provided with an extremely low-impedance path to ground. This connection must be tied externally to all other chip ground connections. The user must provide adequate external decoupling capacitors between PLLP_VDD and PLLP_GND. PLL Ground--The PLL ground should be provided with an extremely low-impedance path to ground. This connection must be tied externally to all other chip ground connections. The user must provide adequate external decoupling capacitors between PLLD_VDD and PLLD_GND. Core Ground--The Core ground should be provided with an extremely low-impedance path to ground. This connection must be tied externally to all other chip ground connections. The user must provide adequate external decoupling capacitors. SHI, ESAI, ESAI_1, WDT and Timer I/O Ground--IO_GND is the ground for the SHI, ESAI, ESAI_1, WDT and Timer I/O. This connection must be tied externally to all other chip ground connections. The user must provide adequate external decoupling capacitors. PLLP_GND(1) PLLD_GND(1) CORE_GND(4) IO_GND(2) Freescale Semiconductor PRELIMINARY 5 Signal Groupings 3.3 SCAN Table 6. SCAN signals Signal Name SCAN Type Input State during Reset Input Signal Description SCAN--Manufacturing test pin. This pin must be connected to ground. 3.4 Clock and PLL Table 7. Clock and PLL Signals Signal Name EXTAL XTAL PINIT/NMI Type Input Output Input State during Reset Input Signal Description External Clock / Crystal Input--An external clock source must be connected to EXTAL in order to supply the clock to the internal clock generator and PLL. Chip Driven Crystal Output--Connects the internal Crystal Oscillator output to an external crystal. If an external clock is used, leave XTAL unconnected. Input PLL Initial/Nonmaskable Interrupt--During assertion of RESET, the value of PINIT/NMI is written into the PLL Enable (PEN) bit of the PLL control register, determining whether the PLL is enabled or disabled. After RESET de-assertion and during normal instruction processing, the PINIT/NMI Schmitt-trigger input is a negative-edge-triggered nonmaskable interrupt (NMI) request internally synchronized to the internal system clock. This pin has an internal pull up resistor. This input is 5 V tolerant. 3.5 Interrupt and Mode Control The interrupt and mode control signals select the chip's operating mode as it comes out of hardware reset. After RESET is deasserted, these inputs are hardware interrupt request lines. Table 8. Interrupt and Mode Control Signal Name MODA/IRQA Type Input State during Reset MODA Input Signal Description Mode Select A/External Interrupt Request A--MODA/IRQA is an active-low Schmitt-trigger input, internally synchronized to the DSP clock. MODA/IRQA selects the initial chip operating mode during hardware reset and becomes a level-sensitive or negative-edgetriggered, maskable interrupt request input during normal instruction processing. This pin can also be programmed as GPIO. MODA, MODB, MODC, and MODD select one of 16 initial chip operating modes, latched into the OMR when the RESET signal is de-asserted. If the processor is in the stop standby state and the MODA/IRQA pin is pulled to GND, the processor will exit the stop state. This pin has an internal pull up resistor. This input is 5 V tolerant. 6 PRELIMINARY Freescale Semiconductor Signal Groupings Table 8. Interrupt and Mode Control (Continued) Signal Name PH0 Type Input, output, or disconnected Input MODB Input State during Reset Signal Description Port H0--When the MODA/IRQA is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. Mode Select B/External Interrupt Request B--MODB/IRQB is an active-low Schmitt-trigger input, internally synchronized to the DSP clock. MODB/IRQB selects the initial chip operating mode during hardware reset and becomes a level-sensitive or negative-edgetriggered, maskable interrupt request input during normal instruction processing. This pin can also be programmed as GPIO. MODA, MODB, MODC, and MODD select one of 16 initial chip operating modes, latched into OMR when the RESET signal is de-asserted. This pin has an internal pull up resistor. This input is 5 V tolerant. PH1 Input, output, or disconnected Input MODC Input Port H1--When the MODB/IRQB is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. Mode Select C/External Interrupt Request C--MODC/IRQC is an active-low Schmitt-trigger input, internally synchronized to the DSP clock. MODC/IRQC selects the initial chip operating mode during hardware reset and becomes a level-sensitive or negative-edgetriggered, maskable interrupt request input during normal instruction processing. This pin can also be programmed as GPIO. MODA, MODB, MODC, and MODD select one of 16 initial chip operating modes, latched into OMR when the RESET signal is de-asserted. This pin has an internal pull up resistor. This input is 5 V tolerant. PH2 Input, output, or disconnected Input MODD Input Port H2--When the MODC/IRQC is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. Mode Select D/External Interrupt Request D--MODD/IRQD is an active-low Schmitt-trigger input, internally synchronized to the DSP clock. MODD/IRQD selects the initial chip operating mode during hardware reset and becomes a level-sensitive or negative-edgetriggered, maskable interrupt request input during normal instruction processing. This pin can also be programmed as GPIO. MODA, MODB, MODC, and MODD select one of 16 initial chip operating modes, latched into OMR when the RESET signal is de-asserted. This pin has an internal pull up resistor. This input is 5 V tolerant. PH3 Input, output, or disconnected Port H3--When the MODD/IRQD is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. MODB/IRQB MODC/IRQC MODD/IRQD Freescale Semiconductor PRELIMINARY 7 Signal Groupings Table 8. Interrupt and Mode Control (Continued) Signal Name RESET Type Input State during Reset Input Signal Description Reset--RESET is an active-low, Schmitt-trigger input. When asserted, the chip is placed in the Reset state and the internal phase generator is reset. The Schmitt-trigger input allows a slowly rising input (such as a capacitor charging) to reset the chip reliably. When the RESET signal is de-asserted, the initial chip operating mode is latched from the MODA, MODB, MODC, and MODD inputs. The RESET signal must be asserted during power up. A stable EXTAL signal must be supplied while RESET is being asserted. This pin has an internal pull up resistor. This input is 5 V tolerant. 3.6 Serial Host Interface The SHI has five I/O signals that can be configured to allow the SHI to operate in either SPI or I2C mode. Table 9. Serial Host Interface Signals Signal Name SCK Signal Type Input or output State during Reset Tri-stated Signal Description SPI Serial Clock--The SCK signal is an output when the SPI is configured as a master and a Schmitt-trigger input when the SPI is configured as a slave. When the SPI is configured as a master, the SCK signal is derived from the internal SHI clock generator. When the SPI is configured as a slave, the SCK signal is an input, and the clock signal from the external master synchronizes the data transfer. The SCK signal is ignored by the SPI if it is defined as a slave and the slave select (SS) signal is not asserted. In both the master and slave SPI devices, data is shifted on one edge of the SCK signal and is sampled on the opposite edge where data is stable. Edge polarity is determined by the SPI transfer protocol. I2C Serial Clock--SCL carries the clock for I2C bus transactions in the I2C mode. SCL is a Schmitt-trigger input when configured as a slave and an open-drain output when configured as a master. SCL should be connected to VDD through an external pull-up resistor according to the I2C specifications. This signal is tri-stated during hardware, software, and individual reset. This pin has an internal pull up resistor. This input is 5 V tolerant. SCL Input or output 8 PRELIMINARY Freescale Semiconductor Signal Groupings Table 9. Serial Host Interface Signals (Continued) Signal Name MISO Signal Type Input or output State during Reset Tri-stated Signal Description SPI Master-In-Slave-Out--When the SPI is configured as a master, MISO is the master data input line. The MISO signal is used in conjunction with the MOSI signal for transmitting and receiving serial data. This signal is a Schmitt-trigger input when configured for the SPI Master mode, an output when configured for the SPI Slave mode, and tri-stated if configured for the SPI Slave mode when SS is de-asserted. An external pull-up resistor is not required for SPI operation. I2C Data and Acknowledge--In I2C mode, SDA is a Schmitt-trigger input when receiving and an open-drain output when transmitting. SDA should be connected to VDD through a pull-up resistor. SDA carries the data for I2C transactions. The data in SDA must be stable during the high period of SCL. The data in SDA is only allowed to change when SCL is low. When the bus is free, SDA is high. The SDA line is only allowed to change during the time SCL is high in the case of start and stop events. A high-to-low transition of the SDA line while SCL is high is a unique situation, and is defined as the start event. A low-to-high transition of SDA while SCL is high is a unique situation defined as the stop event. This signal is tri-stated during hardware, software, and individual reset. Thus, there is no need for an external pull-up in this state. This pin has an internal pull up resistor. This input is 5 V tolerant. MOSI Input or output Tri-stated SPI Master-Out-Slave-In--When the SPI is configured as a master, MOSI is the master data output line. The MOSI signal is used in conjunction with the MISO signal for transmitting and receiving serial data. MOSI is the slave data input line when the SPI is configured as a slave. This signal is a Schmitt-trigger input when configured for the SPI Slave mode. I2C Slave Address 0--This signal uses a Schmitt-trigger input when configured for the I2C mode. When configured for I2C slave mode, the HA0 signal is used to form the slave device address. HA0 is ignored when configured for the I2C master mode. This signal is tri-stated during hardware, software, and individual reset. Thus, there is no need for an external pull-up in this state. This pin has an internal pull up resistor. This input is 5 V tolerant. SS Input Ignored Input SPI Slave Select--This signal is an active low Schmitt-trigger input when configured for the SPI mode. When configured for the SPI Slave mode, this signal is used to enable the SPI slave for transfer. When configured for the SPI master mode, this signal should be kept de-asserted (pulled high). If it is asserted while configured as SPI master, a bus error condition is flagged. If SS is de-asserted, the SHI ignores SCK clocks and keeps the MISO output signal in the high-impedance state. I2C Slave Address 2--This signal uses a Schmitt-trigger input when configured for the I2C mode. When configured for the I2C Slave mode, the HA2 signal is used to form the slave device address. HA2 is ignored in the I2C master mode. This pin has an internal pull up resistor. This input is 5 V tolerant. SDA Input or opendrain output HA0 Input HA2 Input Freescale Semiconductor PRELIMINARY 9 Signal Groupings Table 9. Serial Host Interface Signals (Continued) Signal Name HREQ Signal Type Input or Output State during Reset Tri-stated Signal Description Host Request--This signal is an active low Schmitt-trigger input when configured for the master mode but an active low output when configured for the slave mode. When configured for the slave mode, HREQ is asserted to indicate that the SHI is ready for the next data word transfer and de-asserted at the first clock pulse of the new data word transfer. When configured for the master mode, HREQ is an input. When asserted by the external slave device, it will trigger the start of the data word transfer by the master. After finishing the data word transfer, the master will await the next assertion of HREQ to proceed to the next transfer. This pin can also be programmed as GPIO. Port H4--When HREQ is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. This pin has an internal pull up resistor. PH4 Input, output, or disconnected This input is 5 V tolerant. 3.7 Enhanced Serial Audio Interface Table 10. Enhanced Serial Audio Interface Signals Signal Name HCKR Signal Type Input or output State during Reset GPIO disconnected Signal Description High Frequency Clock for Receiver--When programmed as an input, this signal provides a high frequency clock source for the ESAI receiver as an alternate to the DSP core clock. When programmed as an output, this signal can serve as a high-frequency sample clock (e.g., for external digital to analog converters [DACs]) or as an additional system clock. Port C2--When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. This pin has an internal pull up resistor. This input is 5 V tolerant. PC2 Input, output, or disconnected 10 PRELIMINARY Freescale Semiconductor Signal Groupings Table 10. Enhanced Serial Audio Interface Signals (Continued) Signal Name HCKT Signal Type Input or output State during Reset GPIO disconnected Signal Description High Frequency Clock for Transmitter--When programmed as an input, this signal provides a high frequency clock source for the ESAI transmitter as an alternate to the DSP core clock. When programmed as an output, this signal can serve as a high frequency sample clock (e.g., for external DACs) or as an additional system clock. Port C5--When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. This pin has an internal pull up resistor. This input is 5 V tolerant. FSR Input or output GPIO disconnected Frame Sync for Receiver--This is the receiver frame sync input/output signal. In the asynchronous mode (SYN=0), the FSR pin operates as the frame sync input or output used by all the enabled receivers. In the synchronous mode (SYN=1), it operates as either the serial flag 1 pin (TEBE=0), or as the transmitter external buffer enable control (TEBE=1, RFSD=1). When this pin is configured as serial flag pin, its direction is determined by the RFSD bit in the RCCR register. When configured as the output flag OF1, this pin will reflect the value of the OF1 bit in the SAICR register, and the data in the OF1 bit will show up at the pin synchronized to the frame sync in normal mode or the slot in network mode. When configured as the input flag IF1, the data value at the pin will be stored in the IF1 bit in the SAISR register, synchronized by the frame sync in normal mode or the slot in network mode. PC1 Input, output, or disconnected Port C1--When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. Internal Pull down resistor. This input is 5 V tolerant. PC5 Input, output, or disconnected Freescale Semiconductor PRELIMINARY 11 Signal Groupings Table 10. Enhanced Serial Audio Interface Signals (Continued) Signal Name FST Signal Type Input or output State during Reset GPIO disconnected Signal Description Frame Sync for Transmitter--This is the transmitter frame sync input/output signal. For synchronous mode, this signal is the frame sync for both transmitters and receivers. For asynchronous mode, FST is the frame sync for the transmitters only. The direction is determined by the transmitter frame sync direction (TFSD) bit in the ESAI transmit clock control register (TCCR). Port C4--When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. Internal Pull down resistor. This input is 5 V tolerant. SCKR Input or output GPIO disconnected Receiver Serial Clock--SCKR provides the receiver serial bit clock for the ESAI. The SCKR operates as a clock input or output used by all the enabled receivers in the asynchronous mode (SYN=0), or as serial flag 0 pin in the synchronous mode (SYN=1). When this pin is configured as serial flag pin, its direction is determined by the RCKD bit in the RCCR register. When configured as the output flag OF0, this pin will reflect the value of the OF0 bit in the SAICR register, and the data in the OF0 bit will show up at the pin synchronized to the frame sync in normal mode or the slot in network mode. When configured as the input flag IF0, the data value at the pin will be stored in the IF0 bit in the SAISR register, synchronized by the frame sync in normal mode or the slot in network mode. PC0 Input, output, or disconnected Port C0--When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. Internal Pull down resistor. This input is 5 V tolerant. SCKT Input or output GPIO disconnected Transmitter Serial Clock--This signal provides the serial bit rate clock for the ESAI. SCKT is a clock input or output used by all enabled transmitters and receivers in synchronous mode, or by all enabled transmitters in asynchronous mode. Port C3--When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. Internal Pull down resistor. This input is 5 V tolerant. PC4 Input, output, or disconnected PC3 Input, output, or disconnected 12 PRELIMINARY Freescale Semiconductor Signal Groupings Table 10. Enhanced Serial Audio Interface Signals (Continued) Signal Name SDO5 Signal Type Output State during Reset GPIO disconnected Signal Description Serial Data Output 5--When programmed as a transmitter, SDO5 is used to transmit data from the TX5 serial transmit shift register. Serial Data Input 0--When programmed as a receiver, SDI0 is used to receive serial data into the RX0 serial receive shift register. Port C6--When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. Internal Pull down resistor. This input is 5 V tolerant. SDO4 Output GPIO disconnected Serial Data Output 4--When programmed as a transmitter, SDO4 is used to transmit data from the TX4 serial transmit shift register. Serial Data Input 1--When programmed as a receiver, SDI1 is used to receive serial data into the RX1 serial receive shift register. Port C7--When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. Internal Pull down resistor. This input is 5 V tolerant. SDO3 Output GPIO disconnected Serial Data Output 3--When programmed as a transmitter, SDO3 is used to transmit data from the TX3 serial transmit shift register. Serial Data Input 2--When programmed as a receiver, SDI2 is used to receive serial data into the RX2 serial receive shift register. Port C8--When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. Internal Pull down resistor. This input is 5 V tolerant. SDI0 Input PC6 Input, output, or disconnected SDI1 Input PC7 Input, output, or disconnected SDI2 Input PC8 Input, output, or disconnected Freescale Semiconductor PRELIMINARY 13 Signal Groupings Table 10. Enhanced Serial Audio Interface Signals (Continued) Signal Name SDO2 Signal Type Output State during Reset GPIO disconnected Signal Description Serial Data Output 2--When programmed as a transmitter, SDO2 is used to transmit data from the TX2 serial transmit shift register Serial Data Input 3--When programmed as a receiver, SDI3 is used to receive serial data into the RX3 serial receive shift register. Port C9--When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. Internal Pull down resistor. This input is 5 V tolerant. SDO1 PC10 Output Input, output, or disconnected GPIO disconnected Serial Data Output 1--SDO1 is used to transmit data from the TX1 serial transmit shift register. Port C10--When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. Internal Pull down resistor. This input is 5 V tolerant. SDO0 PC11 Output Input, output, or disconnected GPIO disconnected Serial Data Output 0--SDO0 is used to transmit data from the TX0 serial transmit shift register. Port C11--When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. Internal Pull down resistor. This input is 5 V tolerant. SDI3 Input PC9 Input, output, or disconnected 14 PRELIMINARY Freescale Semiconductor Signal Groupings 3.8 Enhanced Serial Audio Interface_1 Table 11. Enhanced Serial Audio Interface_1 Signals Signal Name HCKR_1 Signal Type Input or output State during Signal Description Reset GPIO disconnected High Frequency Clock for Receiver--When programmed as an input, this signal provides a high frequency clock source for the ESAI_1 receiver as an alternate to the DSP core clock. When programmed as an output, this signal can serve as a high-frequency sample clock (e.g., for external digital to analog converters [DACs]) or as an additional system clock. Port E2--When the ESAI_1 is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. Internal Pull down resistor. This input is 5 V tolerant. PE2 Input, output, or disconnected HCKT_1 Input or output GPIO disconnected High Frequency Clock for Transmitter--When programmed as an input, this signal provides a high frequency clock source for the ESAI_1 transmitter as an alternate to the DSP core clock. When programmed as an output, this signal can serve as a high frequency sample clock (e.g., for external DACs) or as an additional system clock. Port E5--When the ESAI_1 is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. Internal Pull down resistor. This input is 5 V tolerant. PE5 Input, output, or disconnected Freescale Semiconductor PRELIMINARY 15 Signal Groupings Table 11. Enhanced Serial Audio Interface_1 Signals (Continued) Signal Name FSR_1 Signal Type Input or output State during Signal Description Reset GPIO disconnected Frame Sync for Receiver_1--This is the receiver frame sync input/output signal. In the asynchronous mode (SYN=0), the FSR_1 pin operates as the frame sync input or output used by all the enabled receivers. In the synchronous mode (SYN=1), it operates as either the serial flag 1 pin (TEBE=0), or as the transmitter external buffer enable control (TEBE=1, RFSD=1). When this pin is configured as serial flag pin, its direction is determined by the RFSD bit in the RCCR_1 register. When configured as the output flag OF1, this pin will reflect the value of the OF1 bit in the SAICR_1 register, and the data in the OF1 bit will show up at the pin synchronized to the frame sync in normal mode or the slot in network mode. When configured as the input flag IF1, the data value at the pin will be stored in the IF1 bit in the SAISR_1 register, synchronized by the frame sync in normal mode or the slot in network mode. PE1 Input, output, or disconnected Port E1--When the ESAI_1 is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. Internal Pull down resistor. This input is 5 V tolerant FST_1 Input or output GPIO disconnected Frame Sync for Transmitter_1--This is the transmitter frame sync input/output signal. For synchronous mode, this signal is the frame sync for both transmitters and receivers. For asynchronous mode, FST_1 is the frame sync for the transmitters only. The direction is determined by the transmitter frame sync direction (TFSD) bit in the ESAI_1 transmit clock control register (TCCR_1). PE4 Input, output, or disconnected Port E4--When the ESAI_1 is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. Internal Pull down resistor. This input is 5 V tolerant. 16 PRELIMINARY Freescale Semiconductor Signal Groupings Table 11. Enhanced Serial Audio Interface_1 Signals (Continued) Signal Name SCKR_1 Signal Type Input or output State during Signal Description Reset GPIO disconnected Receiver Serial Clock_1--SCKR_1 provides the receiver serial bit clock for the ESAI_1. The SCKR_1 operates as a clock input or output used by all the enabled receivers in the asynchronous mode (SYN=0), or as serial flag 0 pin in the synchronous mode (SYN=1). When this pin is configured as serial flag pin, its direction is determined by the RCKD bit in the RCCR_1 register. When configured as the output flag OF0, this pin will reflect the value of the OF0 bit in the SAICR_1 register, and the data in the OF0 bit will show up at the pin synchronized to the frame sync in normal mode or the slot in network mode. When configured as the input flag IF0, the data value at the pin will be stored in the IF0 bit in the SAISR_1 register, synchronized by the frame sync in normal mode or the slot in network mode. PE0 Input, output, or disconnected Port E0--When the ESAI_1 is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. Internal Pull down resistor. This input is 5 V tolerant SCKT_1 Input or output GPIO disconnected Transmitter Serial Clock_1--This signal provides the serial bit rate clock for the ESAI_1. SCKT_1 is a clock input or output used by all enabled transmitters and receivers in synchronous mode, or by all enabled transmitters in asynchronous mode. Port E3--When the ESAI_1 is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. Internal Pull down resistor. This input is 5 V tolerant PE3 Input, output, or disconnected Freescale Semiconductor PRELIMINARY 17 Signal Groupings Table 11. Enhanced Serial Audio Interface_1 Signals (Continued) Signal Name SDO5_1 Signal Type Output State during Signal Description Reset GPIO disconnected Serial Data Output 5_1--When programmed as a transmitter, SDO5_1 is used to transmit data from the TX5 serial transmit shift register. Serial Data Input 0_1--When programmed as a receiver, SDI0_1 is used to receive serial data into the RX0 serial receive shift register. Port E6--When the ESAI_1 is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. Internal Pull down resistor. This input is 5 V tolerant SDI0_1 Input PE6 Input, output, or disconnected SDO4_1 Output GPIO disconnected Serial Data Output 4_1--When programmed as a transmitter, SDO4_1 is used to transmit data from the TX4 serial transmit shift register. Serial Data Input 1_1--When programmed as a receiver, SDI1_1 is used to receive serial data into the RX1 serial receive shift register. Port E7--When the ESAI_1 is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. Internal Pull down resistor. This input is 5 V tolerant. SDI1_1 Input PE7 Input, output, or disconnected SDO3_1 Output GPIO disconnected Serial Data Output 3--When programmed as a transmitter, SDO3_1 is used to transmit data from the TX3 serial transmit shift register. Serial Data Input 2--When programmed as a receiver, SDI2_1 is used to receive serial data into the RX2 serial receive shift register. Port E8--When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. Internal Pull down resistor. This input is 5 V tolerant. SDI2_1 Input PE8 Input, output, or disconnected 18 PRELIMINARY Freescale Semiconductor Signal Groupings Table 11. Enhanced Serial Audio Interface_1 Signals (Continued) Signal Name SDO2_1 Signal Type Output State during Signal Description Reset GPIO disconnected Serial Data Output 2--When programmed as a transmitter, SDO2_1 is used to transmit data from the TX2 serial transmit shift register. Serial Data Input 3--When programmed as a receiver, SDI3_1 is used to receive serial data into the RX3 serial receive shift register. Port E9--When the ESAI_1 is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. Internal Pull down resistor. This input is 5 V tolerant. SDI3_1 Input PE9 Input, output, or disconnected SDO1_1 PE10 Output Input, output, or disconnected GPIO disconnected Serial Data Output 1--SDO1_1 is used to transmit data from the TX1 serial transmit shift register. Port E10--When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. Internal Pull down resistor. This input is 5 V tolerant. SDO0_1 PE11 Output Input, output, or disconnected GPIO disconnected Serial Data Output 0--SDO0_1 is used to transmit data from the TX0 serial transmit shift register. Port E11--When the ESAI_1 is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. Internal Pull down resistor. This input is 5 V tolerant. 3.9 Dedicated GPIO - Port G Table 12. Dedicated GPIO - Port G Signals Signal Name PG0 Type Input, output, or disconnected State During Reset GPIO disconnected Signal Description Port G0--This signal is individually programmable as input, output, or internally disconnected. Internal Pull down resistor. This input is 5 V tolerant Freescale Semiconductor PRELIMINARY 19 Signal Groupings Table 12. Dedicated GPIO - Port G Signals (Continued) Signal Name PG1 Type Input, output, or disconnected State During Reset GPIO disconnected Signal Description Port G1--This signal is individually programmable as input, output, or internally disconnected. Internal Pull down resistor. This input is 5 V tolerant PG2 Input, output, or disconnected GPIO disconnected Port G2--This signal is individually programmable as input, output, or internally disconnected. Internal Pull down resistor. This input is 5 V tolerant PG3 Input, output, or disconnected GPIO disconnected Port G3--This signal is individually programmable as input, output, or internally disconnected. Internal Pull down resistor. This input is 5 V tolerant PG4 Input, output, or disconnected GPIO disconnected Port G4--This signal is individually programmable as input, output, or internally disconnected. Internal Pull down resistor. This input is 5 V tolerant PG5 Input, output, or disconnected GPIO disconnected Port G5--This signal is individually programmable as input, output, or internally disconnected. Internal Pull down resistor. This input is 5 V tolerant PG6 Input, output, or disconnected GPIO disconnected Port G6--This signal is individually programmable as input, output, or internally disconnected. Internal Pull down resistor. This input is 5 V tolerant PG7 Input, output, or disconnected GPIO disconnected Port G7--This signal is individually programmable as input, output, or internally disconnected. Internal Pull down resistor. This input is 5 V tolerant PG8 Input, output, or disconnected GPIO disconnected Port G8--This signal is individually programmable as input, output, or internally disconnected. Internal Pull down resistor. This input is 5 V tolerant 20 PRELIMINARY Freescale Semiconductor Signal Groupings Table 12. Dedicated GPIO - Port G Signals (Continued) Signal Name PG9 Type Input, output, or disconnected State During Reset GPIO disconnected Signal Description Port G9--This signal is individually programmable as input, output, or internally disconnected. Internal Pull down resistor. This input is 5 V tolerant PG10 Input, output, or disconnected GPIO disconnected Port G10--This signal is individually programmable as input, output, or internally disconnected. Internal Pull down resistor. This input is 5 V tolerant PG11 Input, output, or disconnected GPIO disconnected Port G11--This signal is individually programmable as input, output, or internally disconnected. Internal Pull down resistor. This input is 5 V tolerant PG12 Input, output, or disconnected GPIO disconnected Port G12--This signal is individually programmable as input, output, or internally disconnected. Internal Pull down resistor. This input is 5 V tolerant PG13 Input, output, or disconnected GPIO disconnected Port G13--This signal is individually programmable as input, output, or internally disconnected. Internal Pull down resistor. This input is 5 V tolerant PG14 Input, output, or disconnected GPIO disconnected Port G14--This signal is individually programmable as input, output, or internally disconnected. Internal Pull down resistor. This input is 5 V tolerant Freescale Semiconductor PRELIMINARY 21 Signal Groupings 3.10 Timer Table 13. Timer Signal Signal Name TIO0 Type Input or Output State during Reset Signal Description GPIO Input Timer 0 Schmitt-Trigger Input/Output--When timer 0 functions as an external event counter or in measurement mode, TIO0 is used as input. When timer 0 functions in watchdog, timer, or pulse modulation mode, TIO0 is used as output. The default mode after reset is GPIO input. This can be changed to output or configured as a timer input/output through the timer 0 control/status register (TCSR0). If TIO0 is not being used, it is recommended to either define it as GPIO output immediately at the beginning of operation or leave it defined as GPIO input. Internal Pull down resistor. This input is 5 V tolerant TIO1 Input or Output Watchdog Timer Output Timer 1 Schmitt-Trigger Input/Output--When timer 1 functions as an external event counter or in measurement mode, TIO1 is used as input. When timer 1 functions in watchdog, timer, or pulse modulation mode, TIO1 is used as output. The default mode after reset is GPIO input. This can be changed to output or configured as a timer input/output through the timer 1control/status register (TCSR1). If TIO1 is not being used, it is recommended to either define it as GPIO output immediately at the beginning of operation or leave it defined as GPIO input. WDT Output WDT--When this pin is configured as a hardware watchdog timer pin, this signal is asserted low when the hardware watchdog timer counts down to zero. Internal Pull down resistor. This input is 5 V tolerant TIO2 Input or Output PLOCK Output Timer 2 Schmitt-Trigger Input/Output--When timer 2 functions as an external event counter or in measurement mode, TIO2 is used as input. When timer 2 functions in watchdog, timer, or pulse modulation mode, TIO2 is used as output. The default mode after reset is GPIO input. This can be changed to output or configured as a timer input/output through the timer control/status register (TCSR2). If TIO2 is not being used, it is recommended to either define it as GPIO output immediately at the beginning of operation or leave it defined as GPIO input . 22 PRELIMINARY Freescale Semiconductor Signal Groupings Table 13. Timer Signal (Continued) Signal Name PLOCK Type Output State during Reset Signal Description PLOCK--When this pin is configured as a PLL lock pin, this signal is asserted high when the on-chip PLL enabled and locked and deasserted when the PLL enabled and unlocked. This pin is also asserted high when the PLL is disabled. Internal Pull down resistor. This input is 5 V tolerant 3.11 JTAG/OnCE Interface Table 14. JTAG/OnCE Interface Signal Name TCK Signal Type Input State during Reset Input Signal Description Test Clock--TCK is a test clock input signal used to synchronize the JTAG test logic. Internal Pull up resistor. This input is 5 V tolerant. TDI Input Input Test Data Input--TDI is a test data serial input signal used for test instructions and data. TDI is sampled on the rising edge of TCK. Internal Pull up resistor. This input is 5 V tolerant. TDO Output Tri-stated Test Data Output--TDO is a test data serial output signal used for test instructions and data. TDO is tri-statable and is actively driven in the shift-IR and shift-DR controller states. TDO changes on the falling edge of TCK. Test Mode Select--TMS is an input signal used to sequence the test controller's state machine. TMS is sampled on the rising edge of TCK. Internal Pull up resistor. This input is 5 V tolerant. TMS Input Input Freescale Semiconductor PRELIMINARY 23 Maximum Ratings 4 Maximum Ratings Caution This device contains circuitry protecting against damage due to high static voltage or electrical fields. However, normal precautions should be taken to avoid exceeding maximum voltage ratings. Reliability of operation is enhanced if unused inputs are pulled to an appropriate logic voltage level (e.g., either GND or VDD). The suggested value for a pullup or pulldown resistor is 10 k. NOTE In the calculation of timing requirements, adding a maximum value of one specification to a minimum value of another specification does not yield a reasonable sum. A maximum specification is calculated using a worst case variation of process parameter values in one direction. The minimum specification is calculated using the worst case for the same parameters in the opposite direction. Therefore, a "maximum" value for a specification will never occur in the same device that has a "minimum" value for another specification; adding a maximum to a minimum represents a condition that can never exist. Table 15. Maximum Ratings Rating1 Supply Voltage Symbol VCORE_VDD, VPLLD_VDD VPLLP_VDD, VIO_VDD, VPLLA_VDD, Maximum CORE_VDD power supply ramp time4 All "5.0V tolerant" input voltages Current drain per pin excluding VDD and GND(Except for pads listed below) SCK_SCL TDO Operating temperature range3 Tr VIN I ISCK IJTAG TJ TSTG Value1, 2 Unit V -0.3 to + 1.6 -0.3 to + 4.0 10 GND - 0.3 to 6V 12 16 24 80 LQFP = 90 52 LQFP = 95 V ms V mA mA ma C C V V Storage temperature ESD protected voltage (Human Body Model) ESD protected voltage (Machine Model) Note: -55 to +125 1250 75 1. GND = 0 V, TJ = 0C to 95C (52 LQFP) / 0C to 90C (80 LQFP), CL = 50pF 2. Absolute maximum ratings are stress ratings only, and functional operation at the maximum is not guaranteed. Stress beyond the maximum rating may affect device reliability or cause permanent damage to the device. 3. Operating temperature qualified for consumer applications. TJ = TA + JA x Power. 4. If the power supply ramp to full supply time is longer than 10 ms, the POR circuitry will not operate correctly, causing erroneous operation. 24 PRELIMINARY Freescale Semiconductor Power Requirements 5 Power Requirements To prevent high current conditions due to possible improper sequencing of the power supplies, the connection shown below is recommended to be made between the DSP56374 IO_VDD and Core_VDD power pins. IO_VDD External Schottky Diode Core_VDD To prevent a high current condition upon power up, the IO_VDD must be applied ahead of the Core_VDD as shown below if the external Schottky is not used. Core_VDD IO_VDD For correct operation of the internal power on reset logic, the Core_VDD ramp rate (Tr) to full supply must be less than 10 ms. This is shown below. Tr 1.25V 0V Core_VDD Freescale Semiconductor PRELIMINARY 25 Thermal Characteristics 6 Thermal Characteristics Table 16. Thermal Characteristics Characteristic Natural Convection, Junction-to-ambient thermal resistance1,2 Junction-to-case thermal resistance3 Symbol RJA or JA RJC or JC LQFP Values 68 (52 LQFP) 50 (80 LQFP) 17 (52 LQFP) 11 (80 LQFP) Note: 1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. 2. Per SEMI G38-87 and JEDEC JESD51-2 with the single layer board horizontal. 3. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1). Unit C/W C/W 7 DC Electrical Characteristics Table 17. DC Electrical Characteristics Characteristics Supply voltages * Core (Core_VDD) * PLL (PLLD_VDD) Supply voltages * VIO_VDD * PLL (PLLP_VDD) * PLL (PLLA_VDD) Input high voltage * All pins VIH 2.0 -- VIO_VDD+2V V VDDIO 3.14 3.3 3.46 V Symbol VDD Min 1.2 Typ 1.25 Max 1.3 Unit V Note: All 3.3 volt supplies must rise prior to the rise of the 1.25 volt supplies to avoid a high current condition and possible system damage. Input low voltage * All pins Input leakage current Clock pin Input Capacitance (EXTAL) High impedance (off-state) input current (@ 3.46V) Output high voltage IOH = -5 mA. XTAL Pin IOH = -10mA Output low voltage IOH = 5 mA. XTAL Pin IOH = 10mA VIL IIN CIN ITSI VOH -10 2.4 -0.3 -- -- -- 4.7 -- -- 84 -- 0.8 84 V A pF A V VOL -- -- 0.4 V 26 PRELIMINARY Freescale Semiconductor AC Electrical Characteristics Table 17. DC Electrical Characteristics (Continued) Characteristics Internal supply current1 (core only) at internal clock of 150MHz * In Normal mode * In Wait mode * In Stop mode 2 Symbol Min Typ Max Unit ICCI ICCW ICCS ICCI ICCW ICCS CIN -- -- -- 65 16 1.2 100 40 15 mA mA mA Supply current1 (I/O only) at internal clock of 150MHz * In Normal mode * In Wait mode * In Stop mode2 Input capacitance Note: -- -- -- -- 35 36 1.2 -- 60 50 20 10 mA mA uA pF 1. The Current Consumption section provides a formula to compute the estimated current requirements in Normal mode. In order to obtain these results, all inputs must be terminated (i.e., not allowed to float). Measurements are based on synthetic intensive DSP benchmarks. The power consumption numbers in this specification are 90% of the measured results of this benchmark. This reflects typical DSP applications. Typical internal supply current is measured with VCORE_VDD = 1.25V, VDD_IO = 3.3V at TJ = 25C. Maximum internal supply current is measured with VCORE_VDD = 1.30V, VIO_VDD) = 3.46V at TJ = 115C. 2. In order to obtain these results, all inputs, which are not disconnected at Stop mode, must be terminated (i.e., not allowed to float). 8 AC Electrical Characteristics The timing waveforms shown in the AC electrical characteristics section are tested with a VIL maximum of 0.8V and a VIH minimum of 2.0V for all pins. AC timing specifications, which are referenced to a device input signal, are measured in production with respect to the 50% point of the respective input signal's transition. DSP56374 output levels are measured with the production test machine VOL and VOH reference levels set at 1.0V and 1.8V, respectively. 9 Internal Clocks Table 18. INTERNAL CLOCKS2 No. 1 2 3 Characteristics Comparison Frequency Input Clock Frequency Output clock Frequency (with PLL enabled[1] Symbol Fref FIN FOUT Min 5 Typ -- Fref*NR Max 20 Unit MHz Condition Fref = FIN/NR NR is input divider value 75 (Ef x MF x FM)/ (PDF x DF x OD) Ef 50 150 MHz FOUT=FVCO/NO where NO is output divider value 4 5 Output clock Frequency (with PLL disabled[1] Duty Cycle FOUT -- -- 40 150 60 MHz % -- FVCO=300MHz~600MHz Freescale Semiconductor PRELIMINARY 27 Internal Clocks Table 18. INTERNAL CLOCKS2 (Continued) No. Note: 1. Characteristics DF = Division Factor Ef = External frequency MF = Multiplication Factor PDF = Predivision Factor FM= Frequency Multiplier OD = Output Divider For details of internal clock operation, see Chapter 5 of Users Guide. Symbol Min Typ Max Unit Condition 2. 28 PRELIMINARY Freescale Semiconductor External Clock Operation 10 External Clock Operation The DSP56374 system clock is derived from the on-chip oscillator or is externally supplied. To use the on-chip oscillator, connect a crystal and associated resistor/capacitor components to EXTAL and XTAL; an example is shown below. Suggested component values: = 24.576 MHz R = 1 M 10% C (EXTAL)= 18 pF C (XTAL) = 47 pF Calculations are for a 12 - 49 MHz crystal with the following parameters: * shunt capacitance (C0) of 10 pF - 12 pF * series resistance 40 Ohm * drive level of 10 W fosc If the DSP56374 system clock is an externally supplied square wave voltage source, it is connected to EXTAL (Figure 2). When the external square wave source connects to EXTAL, the XTAL pin is not used. VIH EXTAL VIL ETH 6 8 ETL 7 ETC Midpoint Note: The midpoint is 0.5 (VIH + VIL). Figure 2. External Clock Timing Table 19. Clock Operation No. 6 Characteristics EXTAL input high 1 (40% to 60% duty cycle) 7 EXTAL input low1 (40% to 60% duty cycle) 8 EXTAL cycle time * With PLL disabled * With PLL enabled Etc 6.67 50 inf 200 ns Etl 3.33 50 ns Symbol Eth Min 3.33 Max 50 Units ns Freescale Semiconductor PRELIMINARY 29 Reset, Stop, Mode Select, and Interrupt Timing Table 19. Clock Operation (Continued) No. 9 Characteristics Instruction cycle time= ICYC = TC * With PLL disabled * With PLL enabled Note: 4 Symbol Min Max Units Icyc 6.67 6.67 inf 13.33 ns 1. Measured at 50% of the input transition. 2. The indicated duty cycle is for the specified maximum frequency for which a part is rated. The minimum clock high or low time required for correct operation, however, remains the same at lower operating frequencies; therefore, when a lower clock frequency is used, the signal symmetry may vary from the specified duty cycle as long as the minimum high time and low time requirements are met. 11 Reset, Stop, Mode Select, and Interrupt Timing Table 20. Reset, Stop, Mode Select, and Interrupt Timing No. 10 11 Characteristics Delay from RESET assertion to all pins at reset value3 Required RESET duration4 * Power on, external clock generator, PLL disabled * Power on, external clock generator, PLL enabled 13 Syn reset deassert delay time * Minimum * Maximum (PLL enabled) 14 15 16 17 18 Mode select setup time Mode select hold time Minimum edge-triggered interrupt request assertion width Minimum edge-triggered interrupt request deassertion width Delay from interrupt trigger to interrupt code execution 2 xTC 2 xTC 10 x TC + 5 2x TC (2xTC)+TLOCK 13.4 5.0 10.0 10.0 13.4 13.4 72 -- -- -- -- -- -- -- ns ms ns ns ns ns ns 2 xTC 2 x TC 13.4 13.4 -- -- ns ns Expression -- Min -- Max 11 Unit ns 30 PRELIMINARY Freescale Semiconductor Reset, Stop, Mode Select, and Interrupt Timing Table 20. Reset, Stop, Mode Select, and Interrupt Timing (Continued) No. 19 Characteristics Duration of level sensitive IRQA assertion to ensure interrupt service (when exiting Stop)1, 2, 3 * PLL is active during Stop and Stop delay is enabled (OMR Bit 6 = 0) * PLL is active during Stop and Stop delay is not enabled (OMR Bit 6 = 1) * PLL is not active during Stop and Stop delay is enabled (OMR Bit 6 = 0) * PLL is not active during Stop and Stop delay is not enabled (OMR Bit 6 = 1) 20 * Delay from IRQA, IRQB, IRQC, IRQD, NMI assertion to general-purpose transfer output valid caused by first interrupt instruction execution1 Interrupt Requests Rate1 * ESAI, ESAI_1, SHI, Timer * DMA * IRQ, NMI (edge trigger) * IRQ (level trigger) 22 DMA Requests Rate * Data read from ESAI, ESAI_1, SHI * Data write to ESAI, ESAI_1, SHI * Timer * IRQ, NMI (edge trigger) Note: Expression Min Max Unit 9+(128x TC) 854 -- s 25x TC 165 -- ns 9+(128xTC) + TLOCK (25 x TC) + TLOCK 10 x TC + 3.0 5.7 5 69.0 ms ms ns 21 12 x TC 8 x TC 8 x TC 12 x TC 6 x TC 7 x TC 2 x TC 3 x TC -- -- -- -- -- -- -- -- 80.0 53.0 53.0 80.0 40.0 46.7 13.4 20.0 ns ns ns ns ns ns ns ns 1. When using fast interrupts and IRQA, IRQB, IRQC, and IRQD are defined as level-sensitive, timings 19 through 21 apply to prevent multiple interrupt service. To avoid these timing restrictions, the Edge-triggered mode is recommended when using fast interrupts. Long interrupts are recommended when using Level-sensitive mode. 2. For PLL disable, using external clock (PCTL Bit 16 = 1), no stabilization delay is required and recovery time will be defined by the OMR Bit 6 settings. For PLL enable, (if bet 12 of the PCTL register is 0), the PLL is shutdown during Stop. Recovering from Stop requires the PLL to get locked. The PLL lock procedure duration, PLL Lock Cycles (PLC), may be in the range of 0.5 ms. 3. Periodically sampled and not 100% tested. 4. RESET duration is measured during the time in which RESET is asserted, VDD is valid, and the EXTAL input is active and valid. When the VDD is valid, but the other "required RESET duration" conditions (as specified above) have not been yet met, the device circuitry will be in an uninitialized state that can result in significant power consumption and heat-up. Designs should minimize this state to the shortest possible duration. Freescale Semiconductor PRELIMINARY 31 Reset, Stop, Mode Select, and Interrupt Timing VIH RESET 11 10 All Pins Reset Value 13 Figure 3. Reset Timing IRQA, IRQB, IRQC, IRQD, NMI 19 18 a) First Interrupt Instruction Execution General Purpose I/O 20 IRQA, IRQB, IRQC, IRQD, NMI b) General Purpose I/O Figure 4. External Fast Interrupt Timing IRQA, IRQB, IRQC, IRQD, NMI 16 IRQA, IRQB, IRQC, IRQD, NMI 17 Figure 5. External Interrupt Timing (Negative Edge-Triggered) 32 PRELIMINARY Freescale Semiconductor Reset, Stop, Mode Select, and Interrupt Timing RESET VIH 14 15 MODA, MODB, MODC, MODD, PINIT VIH VIL VIH VIL IRQA, IRQB, IRQC,IRQD, NMI Figure 6. Recovery from Stop State Using IRQA Interrupt Service Freescale Semiconductor PRELIMINARY 33 Serial Host Interface SPI Protocol Timing 12 Serial Host Interface SPI Protocol Timing Table 21. Serial Host Interface SPI Protocol Timing No. 23 Characteristics1,3,4 Minimum serial clock cycle = tSPICC(min) Mode Master Filter Mode Bypassed Very Narrow Narrow Wide XX Tolerable Spike width on data or clock in. -- Bypassed Very Narrow Narrow Wide 24 Serial clock high period Master Bypassed Very Narrow Narrow Wide Slave Bypassed Very Narrow Narrow Wide 25 Serial clock low period Master Bypassed Very Narrow Narrow Wide Slave Bypassed Very Narrow Narrow Wide 26 Serial clock rise/fall time Master Slave -- -- Min 76.0 76.0 200.0 400.0 -- -- -- -- 38.0 38.0 100.0 200.0 33.0 33.0 100.0 200.0 38.0 38.0 100.0 200.0 33.0 33.0 100.0 200.0 -- -- Max -- -- -- -- 0 10 50 100 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 5 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 34 PRELIMINARY Freescale Semiconductor Serial Host Interface SPI Protocol Timing Table 21. Serial Host Interface SPI Protocol Timing (Continued) No. 27 Characteristics1,3,4 SS assertion to first SCK edge CPHA = 0 Mode Slave Filter Mode Bypassed Very Narrow Narrow Wide CPHA = 1 Slave Bypassed Very Narrow Narrow Wide 28 Last SCK edge to SS not asserted Slave Bypassed Very Narrow Narrow Wide 29 Data input valid to SCK edge (data input set-up time) Master /Slave Bypassed Very Narrow Narrow Wide 30 SCK last sampling edge to data input not valid Master /Slave Bypassed Very Narrow Narrow Wide 31 32 33 SS assertion to data out active SS deassertion to data high impedance2 SCK edge to data out valid (data out delay time) Slave Slave Master /Slave -- -- Bypassed Very Narrow Narrow Wide 34 SCK edge to data out not valid (data out hold time) Master /Slave Bypassed Very Narrow Narrow Wide 35 SS assertion to data out valid (CPHA = 0) Slave -- Min 38.4 28.4 0 0 10 0 0 0 12 22 100 200 0 0 0 0 23.2 43.2 73.2 100.0 5 -- -- -- -- -- 5 15 55 105 -- Max -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 9 210 270 376 521 -- -- -- -- 15.0 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Freescale Semiconductor PRELIMINARY 35 Serial Host Interface SPI Protocol Timing Table 21. Serial Host Interface SPI Protocol Timing (Continued) No. 36 Characteristics1,3,4 First SCK sampling edge to HREQ output deassertion Mode Slave Filter Mode Bypassed Very Narrow Narrow Wide 37 Last SCK sampling edge to HREQ output not deasserted (CPHA = 1) Slave Bypassed Very Narrow Narrow Wide 38 39 40 41 SS deassertion to HREQ output not deasserted (CPHA = 0) SS deassertion pulse width (CPHA = 0) HREQ in assertion to first SCK edge HREQ in deassertion to last SCK sampling edge (HREQ in set-up time) (CPHA = 1) First SCK edge to HREQ in not asserted (HREQ in hold time) HREQ assertion width 1. 2. 3. 4. Min 50 60 100 150 57.0 67.0 107.0 157.0 50.0 12.7 63.0 0 Max -- -- -- -- -- -- -- -- -- -- -- -- Unit ns ns ns ns ns ns ns ns ns ns ns ns Slave Slave Master Master -- -- -- -- 42 43 Note: Master Master -- -- 0 20 -- -- ns ns VCORE_VDD = 1.2 5 0.05 V; TJ = 0C to 95C (52 LQFP) / 0C to 90C (80 LQFP), CL = 50 pF Periodically sampled, not 100% tested All times assume noise free inputs. All times assume internal clock frequency of 150 MHz. 36 PRELIMINARY Freescale Semiconductor Serial Host Interface SPI Protocol Timing SS (Input) 25 24 SCK (CPOL = 0) (Output) 24 25 SCK (CPOL = 1) (Output) 29 30 MISO (Input) MSB Valid 23 26 26 26 23 26 29 LSB Valid 30 33 MOSI (Output) 40 HREQ (Input) 43 Figure 7. SPI Master Timing (CPHA = 0) 34 LSB MSB 42 Freescale Semiconductor PRELIMINARY 37 Serial Host Interface SPI Protocol Timing SS (Input) 25 24 SCK (CPOL = 0) (Output) 24 25 SCK (CPOL = 1) (Output) 30 MISO (Input) MSB Valid LSB Valid 23 26 26 23 26 26 29 29 30 33 MOSI (Output) 40 42 HREQ (Input) 43 Figure 8. SPI Master Timing (CPHA = 1) 34 LSB 41 MSB 38 PRELIMINARY Freescale Semiconductor Serial Host Interface SPI Protocol Timing SS (Input) 25 24 SCK (CPOL = 0) (Input) 27 SCK (CPOL = 1) (Input) 35 31 MISO (Output) 29 30 MOSI (Input) HREQ (Output) MSB Valid LSB Valid 23 26 26 39 28 24 25 26 23 26 34 MSB 33 34 32 LSB 29 30 36 38 Figure 9. SPI Slave Timing (CPHA = 0) Freescale Semiconductor PRELIMINARY 39 Serial Host Interface (SHI) I2C Protocol Timing SS (Input) 25 24 SCK (CPOL = 0) (Input) 27 SCK (CPOL = 1) (Input) 33 31 MISO (Output) 29 30 MOSI (Input) HREQ (Output) MSB Valid LSB Valid 23 26 26 28 24 25 26 26 33 MSB 34 32 LSB 29 30 36 37 Figure 10. SPI Slave Timing (CPHA = 1) 13 Serial Host Interface (SHI) I2C Protocol Timing Table 22. SHI I2C Protocol Timing Standard I2C No. XX Characteristics1,2,3,4,5 Tolerable Spike Width on SCL or SDA Filters Bypassed Very Narrow Filters enabled Narrow Filters enabled Wide Fileters enabled. 44 44 45 46 SCL clock frequency SCL clock cycle Bus free time Start condition set-up time FSCL TSCL TBUF TSUSTA Symbol/ Expression -- -- -- -- -- -- 10 4.7 4.7 0 10 50 100 100 -- -- -- -- -- -- -- -- 2.5 1.3 0.6 0 10 50 100 400 -- -- -- ns ns ns ns kHz s s s Standard Min Max Fast-Mode Min Max Unit 40 PRELIMINARY Freescale Semiconductor Serial Host Interface (SHI) I2C Protocol Timing Table 22. SHI I2C Protocol Timing (Continued) Standard I2C No. 47 48 49 50 51 52 53 54 Characteristics1,2,3,4,5 Start condition hold time SCL low period SCL high period SCL and SDA rise time SCL and SDA fall time Data set-up time Data hold time DSP clock frequency * Filters bypassed * Very Narrrow filters enabled * Narrow filters enabled * Wide filters enabled 55 56 57 58 SCL low to data out valid Stop condition setup time HREQ in deassertion to last SCL edge (HREQ in set-up time) First SCL sampling edge to HREQ output deassertion2 * Filters bypassed * Very Narrow filters enabled * Narrow filters enabled * Wide filters enabled 59 Last SCL edge to HREQ output not deasserted2 * Filters bypassed * Very Narrow filters enabled * Narrow filters enabled * Wide filters enabled 60 HREQ in assertion to first SCL edge * Filters bypassed * Very Narrow filters enabled * Narrow filters enabled * Wide filters enabled 61 Note: Symbol/ Expression THD;STA TLOW THIGH TR TF TSU;DAT THD;DAT FOSC Standard Min 4.0 4.7 4.0 -- -- 250 0.0 Max -- -- -- 5.0 5.0 -- -- Fast-Mode Min 0.6 1.3 1.3 -- -- 100 0.0 Max -- -- -- 5.0 5.0 -- 0.9 Unit s s s ns ns ns s MHz MHz MHz MHz s s ns 10.6 10.6 11.8 13.1 TVD;DAT TSU;STO tSU;RQI TNG;RQO 4 x TC + 30 4 x TC + 130 4 x TC + 230 TAS;RQO 2 x TC + 30 2 x TC + 40 2 x TC + 80 44 54 94 144 4 x TC + 50 -- -- -- -- -- 4.0 0.0 -- -- -- -- 3.4 -- -- 28.5 28.5 39.7 61.0 -- 0.6 0.0 -- -- -- -- 0.9 -- -- 57.0 77.0 157.0 257.0 -- -- -- -- 57.0 67.0 157.0 257.0 ns ns ns ns -- -- -- -- 44 54 94 144 -- -- -- -- ns ns ns ns 2 x TC + 130 TAS;RQI 4327 4317 4282 4227 tHO;RQI 0.0 -- -- -- -- -- 927 917 877 827 0.0 -- -- -- -- -- ns ns ns ns ns First SCL edge to HREQ is not asserted (HREQ in hold time.) 1. 2. 3. 4. 5. VCORE_VDD = 1.2 5 0.05 V; TJ = 0C to 95C (52 LQFP) / 0C to 90C (80 LQFP), CL = 50 pF Pull-up resistor: R P (min) = 1.5 kOhm Capacitive load: C b (max) = 50 pF All times assume noise free inputs All times assume internal clock frequency of 150MHz Freescale Semiconductor PRELIMINARY 41 Programming the Serial Clock 14 Programming the Serial Clock The programmed serial clock cycle, T I2CCP , is specified by the value of the HDM[7:0] and HRS bits of the HCKR (SHI clock control register). The expression for T I2CCP is T I2CCP = [TC x 2 x (HDM[7:0] + 1) x (7 x (1 - HRS) + 1)] where HRS is the prescaler rate select bit. When HRS is cleared, the fixed divide-by-eight prescaler is operational. When HRS is set, the prescaler is bypassed. -- HDM[7:0] are the divider modulus select bits. A divide ratio from 1 to 256 (HDM[7:0] = $00 to $FF) may be selected. In I2C mode, the user may select a value for the programmed serial clock cycle from 6 x TC to 4096 x TC (if HDM[7:0] = $FF and HRS = 0) (if HDM[7:0] = $02 and HRS = 1) -- The programmed serial clock cycle (TI2CCP ) should be chosen in order to achieve the desired SCL serial clock cycle (TSCL), as shown in Table 23. Table 23. SCL Serial Clock Cycle (TSCL) Generated as Master Nominal TI2CCP + 3 x TC + 45ns + TR 44 46 SCL 50 45 SDA Stop Start 49 48 51 52 MSB 53 LSB ACK Stop 47 60 HREQ 61 58 57 55 56 59 Figure 11. I2C Timing 42 PRELIMINARY Freescale Semiconductor Enhanced Serial Audio Interface Timing 15 Enhanced Serial Audio Interface Timing Table 24. Enhanced Serial Audio Interface Timing No. 62 Characteristics1, 2, 3 Clock cycle 5 Symbol tSSICC Expression3 4 x Tc 4 x Tc Min 26.4 26.4 Max -- -- Condition4 i ck i ck Unit ns 63 Clock high period * For internal clock * For external clock -- 2 x Tc - 10.0 2 x Tc -- 2 x Tc - 10.0 2 x Tc -- -- 3.4 13.4 -- -- ns 64 Clock low period * For internal clock * For external clock 3.4 13.4 -- -- -- -- 37.0 22.0 37.0 22.0 39.0 24.0 39.0 24.0 36.0 21.0 37.0 22.0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- 29.0 15.0 x ck i ck a x ck i ck a x ck i ck a x ck i ck a x ck i ck a x ck i ck a x ck i ck x ck i ck x ck i ck a x ck i ck a x ck i ck a x ck i ck s x ck i ck s x ck i ck ns 65 SCKR rising edge to FSR out (bl) high ns 66 SCKR rising edge to FSR out (bl) low high6 low6 -- -- -- -- ns 67 SCKR rising edge to FSR out (wr) -- -- -- -- ns 68 SCKR rising edge to FSR out (wr) -- -- -- -- ns 69 SCKR rising edge to FSR out (wl) high -- -- -- -- ns 70 SCKR rising edge to FSR out (wl) low -- -- -- -- ns 71 Data in setup time before SCKR (SCK in synchronous mode) falling edge Data in hold time after SCKR falling edge -- -- 0.0 19.0 ns 72 -- -- 5.0 3.0 ns 73 FSR input (bl, wr) high before SCKR falling edge 6 FSR input (wl) high before SCKR falling edge FSR input hold time after SCKR falling edge -- -- 23.0 1.0 ns 74 -- -- 23.0 1.0 ns 75 -- -- 3.0 0.0 ns 76 Flags input setup before SCKR falling edge -- -- 0.0 19.0 ns 77 Flags input hold time after SCKR falling edge SCKT rising edge to FST out (bl) high -- -- 6.0 0.0 ns 78 -- -- -- -- ns Freescale Semiconductor PRELIMINARY 43 Enhanced Serial Audio Interface Timing Table 24. Enhanced Serial Audio Interface Timing (Continued) No. 79 Characteristics1, 2, 3 SCKT rising edge to FST out (bl) low 6 Symbol -- Expression3 -- Min -- -- Max 31.0 17.0 31.0 17.0 33.0 19.0 30.0 16.0 31.0 17.0 31.0 17.0 34.0 20.0 26.5 21.0 31.0 16.0 34.0 20.0 -- -- -- -- -- -- 27.0 31.0 32.0 18.0 -- 18.0 18.0 Condition4 x ck i ck x ck i ck x ck i ck x ck i ck x ck i ck x ck i ck x ck i ck x ck i ck x ck i ck x ck i ck x ck i ck x ck i ck x ck i ck -- -- x ck i ck Unit ns 80 SCKT rising edge to FST out (wr) high -- -- -- -- ns 81 SCKT rising edge to FST out (wr) low6 -- -- -- -- ns 82 SCKT rising edge to FST out (wl) high -- -- -- -- ns 83 SCKT rising edge to FST out (wl) low -- -- -- -- ns 84 SCKT rising edge to data out enable from high impedance SCKT rising edge to transmitter #0 drive enable assertion SCKT rising edge to data out valid -- -- -- -- ns 85 -- -- -- -- ns 86 -- -- -- -- ns 87 SCKT rising edge to data out high impedance7 SCKT rising edge to transmitter #0 drive enable deassertion7 FST input (bl, wr) setup time before SCKT falling edge6 FST input (wl) setup time before SCKT falling edge FST input hold time after SCKT falling edge -- -- -- -- ns 88 -- -- -- -- ns 89 -- -- 2.0 21.0 ns 90 -- -- 2.0 21.0 ns 91 -- -- 4.0 0.0 ns 92 93 94 FST input (wl) to data out enable from high impedance FST input (wl) to transmitter #0 drive enable assertion Flag output valid after SCKT rising edge -- -- -- -- -- -- -- -- -- -- ns ns ns 95 96 97 HCKR/HCKT clock cycle HCKT input rising edge to SCKT output HCKR input rising edge to SCKR output -- -- -- 2 x TC -- -- 13.4 -- -- ns ns ns 44 PRELIMINARY Freescale Semiconductor Enhanced Serial Audio Interface Timing Table 24. Enhanced Serial Audio Interface Timing (Continued) No. Note: Characteristics1, 2, 3 Symbol Expression3 Min Max Condition4 Unit 1. VCORE_VDD = 1.25 0.05 V; TJ = 0C to 95C (52 LQFP) / 0C to 90C (80 LQFP), CL = 50 pF 2. i ck = internal clock x ck = external clock i ck a = internal clock, asynchronous mode (asynchronous implies that SCKT and SCKR are two different clocks) i ck s = internal clock, synchronous mode (synchronous implies that SCKT and SCKR are the same clock) 3. bl = bit length wl = word length wr = word length relative 4. SCKT(SCKT pin) = transmit clock SCKR(SCKR pin) = receive clock FST(FST pin) = transmit frame sync FSR(FSR pin) = receive frame sync HCKT(HCKT pin) = transmit high frequency clock HCKR(HCKR pin) = receive high frequency clock 5. For the internal clock, the external clock cycle is defined by Icyc and the ESAI control register. 6. The word-relative frame sync signal waveform relative to the clock operates in the same manner as the bit-length frame sync signal waveform, but spreads from one serial clock before first bit clock (same as bit length frame sync signal), until the one before last bit clock of the first word in frame. 7. Periodically sampled and not 100% tested. 8. ESAI_1 specs match those of ESAI. Freescale Semiconductor PRELIMINARY 45 Enhanced Serial Audio Interface Timing 62 63 SCKT (Input/Output) 78 FST (Bit) Out 82 FST (Word) Out 83 79 64 86 84 86 87 First Bit Last Bit Data Out 93 Transmitter #0 Drive Enable (Internal Signal) 89 91 85 88 FST (Bit) In 92 90 FST (Word) In 94 Flags Out See Note 91 Note: In network mode, output flag transitions can occur at the start of each time slot within the frame. In normal mode, the output flag state is asserted for the entire frame period. Figure 12. ESAI Transmitter Timing 46 PRELIMINARY Freescale Semiconductor Enhanced Serial Audio Interface Timing 62 63 SCKR (Input/Output) 65 FSR (Bit) Out 69 FSR (Word) Out 72 71 Data In 73 FSR (Bit) In 74 FSR (Word) In 76 Flags In 77 75 75 First Bit Last Bit 70 64 66 Figure 13. ESAI Receiver Timing Freescale Semiconductor PRELIMINARY 47 Timer Timing HCKT 95 96 SCKT(output) Figure 14. ESAI HCKT Timing HCKR 95 97 SCKR (output) Figure 15. ESAI HCKR Timing 16 Timer Timing Table 25. Timer Timing 150 MHz No. 98 99 TIO Low TIO High Characteristics Expression Min 2 x TC + 2.0 2 x TC + 2.0 15.4 15.4 Max -- -- ns ns Unit Note: VCORE_VDD = 1.25 V 0.05 V; TJ = 0C to 95C (52 LQFP) / 0C to 90C (80 LQFP), CL = 50 pF TIO 98 99 Figure 16. TIO Timer Event Input Restrictions 17 GPIO Timing 48 PRELIMINARY Freescale Semiconductor GPIO Timing Table 26. GPIO Timing No. 100 101 102 103 104 105 106 107 Note: Characteristics1 FOSC edge to GPIO out valid (GPIO out delay time) 2 Expression Min -- -- 2 0 Max 7 7 -- -- -- -- 13.0 13.0 Unit ns ns ns ns ns ns ns ns FOSC edge to GPIO out not valid (GPIO out hold time)2 FOSC In valid to EXTAL edge (GPIO in set-up time) 2 FOSC edge to GPIO in not valid (GPIO in hold time)2 Minimum GPIO pulse high width Minimum GPIO pulse low width GPIO out rise time GPIO out fall time 1. VCORE_VDD = 1.25 V 0.05 V; TJ = -40C to +115C, CL = 50 pF 2. Simulation numbers-subject to change. 2 x TC 2 x TC -- -- 13.4 13.4 -- -- FOSC 100 101 GPIO (Output) 102 GPIO (Input) GPIO (Output) 104 106 105 107 Valid 103 Figure 17. GPIO Timing Freescale Semiconductor PRELIMINARY 49 JTAG Timing 18 JTAG Timing Table 27. JTAG Timing All frequencies No. 108 109 110 111 112 113 114 115 116 117 118 119 Note: Characteristics Min TCK frequency of operation (1/(TC x 3); maximum 10 MHz) TCK cycle time in Crystal mode TCK clock pulse width measured at 1.65 V TCK rise and fall times Boundary scan input data setup time Boundary scan input data hold time TCK low to output data valid TCK low to output high impedance TMS, TDI data setup time TMS, TDI data hold time TCK low to TDO data valid TCK low to TDO high impedance -- 100.0 50.0 -- 15.0 24.0 -- -- 5.0 25.0 -- -- Max 10.0 -- -- 3.0 -- -- 40.0 40.0 -- -- 44.0 44.0 Unit MHz ns ns ns ns ns ns ns ns ns ns ns 1. VCORE_VDD = 1.25 V 0.05 V; TJ = -40C to +95C, CL = 50 pF 2. All timings apply to OnCE module data transfers because it uses the JTAG port as an interface. 109 110 TCK (Input) VIH VM VIL 110 VM 111 111 Figure 18. Test Clock Input Timing Diagram 50 PRELIMINARY Freescale Semiconductor JTAG Timing TCK (Input) VIH VIL 112 113 Data Inputs 114 Data Outputs 115 Data Outputs 114 Data Outputs Input Data Valid Output Data Valid Output Data Valid Figure 19. Debugger Port Timing Diagram TCK (Input) TDI TMS (Input) VIH VIL 116 117 Input Data Valid 118 TDO (Output) 119 TDO (Output) 118 TDO (Output) Output Data Valid Output Data Valid Figure 20. Test Access Port Timing Diagram Freescale Semiconductor PRELIMINARY 51 Watchdog Timer Timing 19 Watchdog Timer Timing Table 28. Watchdog Timer Timing No. 120 121 Characteristics Delay from time-out to fall of TIO1 Delay from timer clear to rise of TIO1 Expression 2 x Tc 2 x Tc Min 13.4 13.4 Max -- -- Unit ns ns 52 PRELIMINARY Freescale Semiconductor Appendix A Package Information Appendix A Package Information DSP56374 Pinout SCKR_1_PE0 HCKR_1_PE2 HCKT_PC5 HCKT_1_PE5 SCKT_1_PE3 FSR_1_PE1 GPIO_PG14 FST_1_PE4 SCKR_PC0 SDO5_PC6 SDO4_PC7 Core_Vdd SCKT_PC3 FSR_PC1 Core_Gnd HCKR_PC2 FST_PC4 IO_Gnd 80 75 74 73 65 71 76 SCAN 62 IO_Vdd MODA_IRQA_PH0 MODB_IRQB_PH1 GPIO_PG13 GPIO_PG12 MODC_IRQC_PH2 MODD_IRQD_PH3 GPIO_PG11 Core_Vdd Core_Gnd GPIO_PG10 GPIO_PG9 HREQ_PH4 SS_HA2 SCK_SCL MISO_SDA MOSI_HA0 GPIO_PG8 GPIO_PG7 IO_Gnd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 68 77 72 79 78 67 66 69 64 63 70 IO_Vdd SDO5_1_PE6 SDO4_1_PE7 SDO3_PC8 SDO2_PC9 SDO1_PC10 SDO0_PC11 SDO3_1_PE8 SDO2_1_PE9 Core_Vdd Core_Gnd SDO1_1_PE10 SDO0_1_PE11 PINIT_NMI IO_Vdd XTAL EXTAL PLLD_Vdd PLLD_Gnd PLLP_Gnd PLLP_Vdd 31 39 PLLA_Vdd 22 23 28 30 34 36 37 26 21 24 25 27 29 PLOCK/TIO2 GPIO_PG6 GPIO_PG5 GPIO_PG4 GPIO_PG3 35 GPIO_PG2 GPIO_PG1 GPIO_PG0 38 32 33 PLLA_Gnd WDT/TIO1 Core_Gnd RESET_B Core_Vdd IO_Vdd TIO00 TDO TMS TCK TDI 40 1.25V Filter 3.3V Figure 21. 80-pin Vdd Connections Freescale Semiconductor PRELIMINARY 53 Appendix A Package Information SCKR_PC0 SDO5_PC6 SDO4_PC7 HCKR_PC2 Core_Vdd FSR_PC1 SCKT_PC3 Core_Gnd FST_PC4 IO_Gnd HCKT_PC5 43 42 48 52 51 50 46 44 49 SCAN 41 IO_Vdd MODA_IRQA_PH0 MODB_IRQB_PH1 MODC_IRQC_PH2 MODD_IRQD_PH3 Core_Vdd Core_Gnd HREQ_PH4 SS_HA2 SCK_SCL MISO_SDA MOSI_HA0 IO_Gnd 1 2 3 4 5 6 7 8 9 10 11 12 13 40 47 45 IO_Vdd 39 38 37 36 35 34 33 32 31 30 29 28 27 SDO3_PC8 SDO2_PC9 SDO1_PC10 SDO0_PC11 Core_Vdd Core_Gnd PINIT_NMI XTAL EXTAL PLLD_Vdd PLLD_Gnd PLLP_Gnd PLLP_Vdd 21 19 20 24 15 16 17 22 23 14 18 PLOCK/TIO2 25 PLLA_Vdd PLLA_Gnd WDT/TIO1 Core_Gnd RESET_B Core_Vdd IO_Vdd TIO00 TDO TMS TCK TDI 26 1.25V Filter 3.3V Figure 22. 52-pin Vdd Connections 19.1 Signal Identification by Pin Number 54 PRELIMINARY Freescale Semiconductor Appendix A Package Information 19.2 Package Information 80 pin package . Freescale Semiconductor PRELIMINARY 55 Appendix A Package Information 56 PRELIMINARY Freescale Semiconductor Appendix A Package Information Freescale Semiconductor PRELIMINARY 57 Appendix A Package Information . 58 PRELIMINARY Freescale Semiconductor Appendix A Package Information 52 pin package Freescale Semiconductor PRELIMINARY 59 Appendix A Package Information 60 PRELIMINARY Freescale Semiconductor Appendix A Package Information Freescale Semiconductor PRELIMINARY 61 Appendix A Package Information 62 PRELIMINARY Freescale Semiconductor Appendix B IBIS Model Appendix B IBIS Model [IBIS ver] [File name] [File Rev] [Date] [Source] [Disclaimer] [Copyright] | |************************************************************************ | Component tpz013g3 |************************************************************************ (Pin) 1 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 signal_name IO_VDD 2 MODA_IRQA_PH0 MODB_IRQB_PH1 GPIO_PG13 GPIO_PG12 MODC_IRQC_PH2 MODD_IRQD_PH3 GPIO_PG11 CORE_VDD CORE_GND GPIO_PG10 GPIO_PG9 HREQ_PH4 SS_HA2 SCK_SCL MISO_SDA MOSI_HA0 GPIO_PG8 GPIO_PG7 IO_GND IO_VDD GPIO_PG6 GPIO_PG5 TDO TDI TCK TMS GPIO_PG4 model_name PVDD2DGZ/PVDD2POC PDU12SDGZ PDU12SDGZ PRD12DGZ PRD12DGZ PDU12SDGZ PDU12SDGZ PRD12DGZ PVDD1DGZ PVSS3DGZ PRD12DGZ PRD12DGZ PDU12SDGZ PDUSDGZ PDU12SDGZ PDU16SDGZ PDU12SDGZ PRD12DGZ PRD12DGZ PVSS3DGZ PVDD2DGZ PRD12DGZ PRD12DGZ PRT24DGZ PDUDGZ PDUDGZ PDUDGZ PRD12DGZ 2.1 tpz013g3.ibs 1.0 07/30/2002 Made By 0.13uu HSPICE model. This information is for modeling purposes only and is not guaranteed. Copyright 2002, Design Service, tsmc, All Rights Reserved. Freescale Semiconductor PRELIMINARY 63 Appendix B IBIS Model 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 TIO0_PB0 WDT_TIO1_PB1 PLOCK_TIO1_PB2 CORE_VDD CORE_GND GPIO_PG3 RESET_B GPIO_PG2 GPIO_PG1 GPIO_PG0 PLLA_VDD PLLA_GND PLLP_VDD PLLP_GND PLLD_GND PLLD_VDD EXTAL XTAL IO_VDD PINIT_NMI SDO0_1_PE11 SDO1_1_PE10 CORE_GND CORE_VDD SDO2_1_PE9 SDO3_1_PE8 SDO0_PC11 SDO1_PC10 SDO2_SDI3_PC9 SDO3_SDI2_PC8 SDO4_1_PE7 SDO5_1_PC6 IO_VDD SCAN HCKT_1_PE5 HCKT_PC5 HCKR_PC2 HCKR_1_PE2 SCKT_1_PE3 SCKT_PC3 SCKR_PC0 SCKR_1_PE0 CORE_GND CORE_VDD PRD12DGZ PRD12DGZ PRD12DGZ PVDD1DGZ PVSS3DGZ PRD12DGZ PDUSDGZ PRD12DGZ PRD12DGZ PRD12DGZ PVDD1P PVSS1P PVDD2DGZ PVSS2P PVSS1P PVDD1PC 1/2 PDX03DGZ 1/2 PDX03DGZ PVDD2DGZ PDUSDGZ PRD12DGZ PRD12DGZ PVSS3DGZ PVDD1DGZ PRD12DGZ PRD12DGZ PRD12DGZ PRD12DGZ PRD12DGZ PRD12DGZ PRD12DGZ PRD12DGZ PVDD2DGZ PDDDGZ PRD12DGZ PRD12DGZ PRD12DGZ PRD12DGZ PRD12DGZ PRD12DGZ PRD12DGZ PRD12DGZ PVSS3DGZ PVDD1DGZ 64 PRELIMINARY Freescale Semiconductor Appendix B IBIS Model 73 74 75 76 77 78 | | [Model] GPIO_PG14 FST_1_PE4 FST_PC4 FSR_PC1 FSR_1_PE1 SDO4_SDI1_PC7 PRD12DGZ PRD12DGZ PRD12DGZ PRD12DGZ PRD12DGZ PRD12DGZ Model prd12dgz |************************************************************************ |************************************************************************ prd12dgz I/O Non-Inverting Active-Low 0.80V 2.00V 1.50V 50.00pF 1.00M 0.000V 4.17pF 3.75pF 4.58pF Model_type Polarity Enable Vinl = Vinh = Vmeas = Cref = Rref = Vref = C_comp | | [Temperature Range] [Pullup Reference] [Pulldown Reference] [POWER Clamp Reference] [GND Clamp Reference] [Pulldown] | voltage | -3.30 -3.10 -2.90 -2.70 -2.50 -2.30 -2.10 -1.90 -1.70 -1.50 -1.00 -0.90 -0.80 0.000A 0.000A 0.000A 0.000A 0.000A -10.00mA 0.000A 0.000A 0.000A -10.00mA -11.00mA -12.00mA -24.00mA I(typ) 25.00 3.30V 0.000V 5.00V 0.000V I(min) 0.000A 0.000A 0.000A 0.000A -10.00mA 0.000A -10.00mA 0.000A 0.000A 0.000A -5.00mA -5.00mA -7.00mA 0.12k 3.00V 0.000V 4.50V 0.000V I(max) 0.000A -10.00mA 0.000A 0.000A 0.000A -10.00mA 0.000A -10.00mA -10.00mA -10.00mA -13.00mA -15.00mA -32.51mA 0.000 3.60V 0.000V 5.50V 0.000V Freescale Semiconductor PRELIMINARY 65 Appendix B IBIS Model -0.70 -0.60 -0.50 -0.40 -0.30 -0.20 -0.10 -0.00 0.10 0.20 0.30 0.40 0.50 0.60 0.70 0.80 0.90 1.00 1.10 1.20 1.30 1.40 1.50 1.60 1.70 1.80 1.90 2.00 2.10 2.20 2.30 2.40 2.50 2.60 2.70 2.80 2.90 3.00 3.10 3.20 3.30 3.40 3.50 3.60 -29.14mA -26.47mA -22.61mA -18.32mA -13.87mA -9.33mA -4.70mA 2.86nA 4.61mA 8.96mA 13.07mA 16.92mA 20.53mA 23.91mA 27.04mA 29.95mA 32.61mA 35.06mA 37.27mA 39.27mA 41.04mA 42.60mA 43.95mA 45.08mA 46.00mA 46.70mA 47.20mA 47.55mA 47.81mA 48.01mA 48.17mA 48.31mA 48.42mA 48.53mA 48.62mA 48.70mA 48.78mA 48.85mA 48.92mA 48.99mA 49.05mA 49.12mA 49.20mA 49.24mA -8.00mA -13.80mA -14.54mA -12.17mA -9.16mA -6.10mA -3.05mA 7.25nA 2.94mA 5.69mA 8.26mA 10.65mA 12.86mA 14.90mA 16.76mA 18.46mA 19.99mA 21.37mA 22.58mA 23.64mA 24.55mA 25.32mA 25.95mA 26.44mA 26.80mA 27.07mA 27.26mA 27.41mA 27.53mA 27.63mA 27.71mA 27.78mA 27.85mA 27.90mA 27.96mA 28.01mA 28.05mA 28.09mA 28.14mA 28.18mA 28.23mA 28.42mA 28.97mA 29.74mA -32.35mA -29.35mA -25.54mA -20.93mA -15.91mA -10.74mA -5.43mA 11.72nA 5.36mA 10.49mA 15.36mA 20.00mA 24.40mA 28.55mA 32.48mA 36.18mA 39.64mA 42.87mA 45.87mA 48.64mA 51.19mA 53.50mA 55.60mA 57.46mA 59.11mA 60.53mA 61.71mA 62.63mA 63.31mA 63.79mA 64.15mA 64.43mA 64.65mA 64.84mA 65.00mA 65.14mA 65.27mA 65.38mA 65.49mA 65.59mA 65.68mA 65.77mA 65.86mA 65.95mA 66 PRELIMINARY Freescale Semiconductor Appendix B IBIS Model 3.70 3.80 3.90 4.00 4.10 4.20 4.30 4.50 4.70 4.90 5.10 5.30 5.50 5.70 5.90 6.10 6.60 | [Pullup] | voltage | -3.30 -3.10 -2.90 -2.70 -2.50 -2.30 -2.10 -1.90 -1.70 -1.50 -1.00 -0.90 -0.80 -0.70 -0.60 -0.50 -0.40 -0.30 -0.20 -0.10 0.00 0.10 0.20 49.31mA 49.40mA 49.61mA 50.41mA 51.65mA 52.87mA 50.78mA 50.67mA 51.17mA 51.85mA 52.75mA 53.86mA 55.21mA 56.82mA 58.68mA 60.78mA 66.91mA 30.57mA 31.13mA 28.60mA 28.66mA 28.72mA 28.80mA 28.89mA 29.12mA 29.42mA 29.83mA 30.37mA 31.02mA 31.82mA 32.77mA 33.86mA 35.10mA 38.73mA 66.04mA 66.12mA 66.22mA 66.33mA 66.49mA 66.72mA 67.28mA 70.40mA 73.03mA 69.12mA 70.18mA 71.45mA 73.05mA 74.98mA 77.25mA 79.83mA 87.50mA I(typ) 0.11A 0.11A 0.10A 97.60mA 92.41mA 87.04mA 81.44mA 75.56mA 69.36mA 62.83mA 48.46mA 43.82mA 38.59mA 33.28mA 28.26mA 23.64mA 19.01mA 14.32mA 9.58mA 4.80mA 34.08uA -4.58mA -8.94mA I(min) 82.01mA 79.25mA 76.07mA 72.55mA 68.70mA 64.55mA 60.13mA 55.45mA 50.52mA 45.36mA 31.37mA 28.63mA 28.69mA 24.97mA 21.04mA 17.11mA 13.34mA 9.87mA 6.53mA 3.23mA 11.20uA -3.08mA -5.98mA I(max) 0.13A 0.13A 0.12A 0.11A 0.11A 0.10A 94.69mA 87.72mA 80.48mA 73.03mA 56.75mA 50.74mA 44.61mA 38.60mA 33.20mA 27.91mA 22.52mA 17.03mA 11.45mA 5.78mA 71.92uA -5.50mA -10.80mA Freescale Semiconductor PRELIMINARY 67 Appendix B IBIS Model 0.30 0.40 0.50 0.60 0.70 0.80 0.90 1.00 1.10 1.20 1.30 1.40 1.50 1.60 1.70 1.80 1.90 2.00 2.10 2.20 2.30 2.40 2.50 2.60 2.70 2.80 2.90 3.00 3.10 3.20 3.30 3.40 3.50 3.60 3.70 3.80 3.90 4.00 4.10 4.20 4.30 4.50 4.70 4.90 -13.04mA -16.89mA -20.50mA -23.86mA -26.98mA -29.87mA -32.53mA -34.96mA -37.16mA -39.15mA -40.92mA -42.48mA -43.83mA -44.98mA -45.94mA -46.72mA -47.35mA -47.86mA -48.29mA -48.65mA -48.97mA -49.25mA -49.50mA -49.72mA -49.92mA -50.11mA -50.28mA -50.44mA -50.59mA -50.74mA -50.88mA -51.01mA -51.14mA -51.27mA -51.42mA -51.84mA -53.78mA -64.80mA -0.29A -1.85A -3.90A -8.00A -12.10A -16.20A -8.72mA -11.27mA -13.66mA -15.87mA -17.92mA -19.80mA -21.51mA -23.06mA -24.45mA -25.68mA -26.75mA -27.66mA -28.43mA -29.05mA -29.53mA -29.90mA -30.20mA -30.45mA -30.66mA -30.85mA -31.02mA -31.17mA -31.31mA -31.44mA -31.56mA -31.67mA -31.78mA -31.88mA -31.98mA -32.08mA -32.20mA -32.75mA -40.35mA -0.14A -0.94A -2.69A -4.48A -6.27A -8.06A -9.85A -11.63A -15.21A -18.79A -22.36A -15.82mA -20.56mA -25.04mA -29.25mA -33.21mA -36.91mA -40.36mA -43.56mA -46.52mA -49.24mA -51.73mA -53.98mA -56.01mA -57.81mA -59.40mA -60.77mA -61.93mA -62.90mA -63.70mA -64.37mA -64.93mA -65.40mA -65.82mA -66.18mA -66.50mA -66.79mA -67.05mA -67.29mA -67.51mA -67.72mA -67.92mA -68.11mA -68.29mA -68.47mA -68.64mA -68.80mA -68.97mA -69.30mA -70.82mA -75.29mA -83.12mA -1.14A -5.39A -9.64A 68 PRELIMINARY Freescale Semiconductor Appendix B IBIS Model 5.10 5.30 5.50 5.70 5.90 6.10 6.60 | [GND_clamp] | voltage | -5.00 -4.80 -4.60 -4.40 -4.20 -4.00 -3.80 -3.60 -3.40 -3.20 -3.00 -2.80 -2.60 -2.40 -2.20 -2.00 -1.80 -1.60 -1.40 -1.20 -1.00 -0.80 -0.60 -0.40 -0.20 -0.00 0.20 0.40 0.60 0.80 1.00 1.20 1.40 -20.30A -24.40A -28.50A -32.60A -36.70A -40.80A -51.05A -25.94A -29.51A -33.09A -36.67A -40.24A -43.82A -52.76A -13.89A -18.15A -22.41A -26.66A -30.92A -35.17A -45.81A I(typ) -85.83A -81.73A -77.63A -73.53A -69.43A -65.33A -61.23A -57.13A -53.03A -48.93A -44.84A -40.74A -36.64A -32.54A -28.45A -24.35A -20.25A -16.15A -12.05A -7.95A -3.85A -0.23A -2.25mA -89.81uA -27.92uA -87.63nA 18.71uA 29.19uA 32.49uA 33.07uA 33.30uA 33.45uA 33.57uA I(min) -77.78A -74.20A -70.62A -67.04A -63.46A -59.88A -56.30A -52.72A -49.14A -45.56A -41.99A -38.42A -34.84A -31.27A -27.69A -24.12A -20.54A -16.97A -13.39A -9.82A -6.24A -2.66A -0.10A -0.52mA -14.70uA -89.05nA 7.31uA 10.25uA 10.67uA 10.78uA 10.86uA 10.92uA 10.97uA I(max) -88.32A -84.06A -79.80A -75.54A -71.28A -67.02A -62.76A -58.50A -54.24A -49.98A -45.73A -41.48A -37.22A -32.97A -28.72A -24.46A -20.21A -15.95A -11.70A -7.44A -3.19A -70.99mA -5.98mA -0.26mA -42.92uA -0.10uA 32.27uA 54.12uA 65.78uA 69.33uA 70.17uA 70.55uA 70.80uA Freescale Semiconductor PRELIMINARY 69 Appendix B IBIS Model 1.60 1.80 2.00 2.20 2.40 2.60 2.80 3.00 3.20 3.40 3.60 3.80 4.00 4.20 4.40 4.60 4.80 5.00 | [POWER_clamp] | voltage | -5.00 -4.90 -4.80 -4.70 -4.60 -4.50 -4.40 -4.30 -4.20 -4.10 -4.00 -3.90 -3.80 -3.70 -3.60 -3.50 -3.40 -3.30 -3.20 -3.10 -3.00 -2.90 33.68uA 33.77uA 33.87uA 33.96uA 34.01uA 34.03uA 34.05uA 34.06uA 34.07uA 34.07uA 34.07uA 34.07uA 34.07uA 34.07uA 34.07uA 34.07uA 34.07uA 34.07uA 11.02uA 11.07uA 11.11uA 11.14uA 11.15uA 11.16uA 11.17uA 11.19uA 11.51uA 10.95uA 10.39uA 9.83uA 9.27uA 8.71uA 8.15uA 7.59uA 7.03uA 6.47uA 70.99uA 71.16uA 71.32uA 71.46uA 71.61uA 71.76uA 71.84uA 71.86uA 71.88uA 71.90uA 71.92uA 71.94uA 71.96uA 71.98uA 72.00uA 72.02uA 72.04uA 72.06uA I(typ) 48.57uA 48.24uA 47.91uA 47.58uA 47.25uA 46.92uA 46.59uA 46.26uA 45.93uA 45.60uA 45.27uA 44.94uA 44.61uA 44.28uA 43.95uA 43.62uA 43.29uA 42.96uA 42.63uA 42.30uA 41.97uA 41.64uA I(min) 16.33uA 16.21uA 16.09uA 15.97uA 15.85uA 15.73uA 15.61uA 15.49uA 15.37uA 15.25uA 15.13uA 15.01uA 14.89uA 14.77uA 14.65uA 14.53uA 14.41uA 14.29uA 14.17uA 14.05uA 13.93uA 13.81uA I(max) 95.57uA 95.07uA 94.57uA 94.07uA 93.57uA 93.07uA 92.57uA 92.07uA 91.57uA 91.07uA 90.57uA 90.07uA 89.57uA 89.07uA 88.57uA 88.07uA 87.57uA 87.07uA 86.57uA 86.07uA 85.57uA 85.07uA 70 PRELIMINARY Freescale Semiconductor Appendix B IBIS Model -2.80 -2.70 -2.60 -2.50 -2.40 -2.30 -2.20 -2.10 -2.00 -1.90 -1.80 -1.70 -1.60 -1.50 -1.40 -1.30 -1.20 -1.10 -1.00 -0.90 -0.80 -0.70 -0.60 -0.50 -0.40 -0.30 -0.20 -0.10 0.00 | [Ramp] | variable dV/dt_r dV/dt_f R_load = 50.00 | 41.31uA 40.98uA 40.65uA 40.32uA 39.99uA 39.66uA 39.33uA 39.00uA 38.67uA 38.34uA 38.01uA 37.68uA 37.35uA 37.02uA 36.71uA 36.42uA 36.15uA 35.89uA 35.66uA 35.45uA 35.26uA 35.09uA 34.93uA 34.80uA 34.68uA 34.59uA 34.50uA 34.43uA 34.37uA 13.69uA 13.57uA 13.45uA 13.33uA 13.21uA 13.09uA 12.97uA 12.85uA 12.73uA 12.61uA 12.49uA 12.37uA 12.25uA 12.15uA 12.05uA 11.95uA 11.87uA 11.79uA 11.72uA 11.66uA 11.60uA 11.55uA 11.51uA 11.47uA 11.43uA 11.41uA 11.38uA 11.36uA 11.34uA 84.57uA 84.07uA 83.57uA 83.07uA 82.57uA 82.07uA 81.57uA 81.07uA 80.57uA 80.07uA 79.57uA 79.07uA 78.57uA 78.07uA 77.57uA 77.07uA 76.57uA 76.07uA 75.57uA 75.10uA 74.67uA 74.28uA 73.93uA 73.61uA 73.34uA 73.10uA 72.89uA 72.72uA 72.57uA typ 1.21/2.06n 1.22/2.51n min 0.85/2.62n 0.78/3.11n max 1.45/1.82n 1.45/2.14n [Rising Waveform] R_fixture = 50.00 V_fixture = 0.000 V_fixture_min = 0.000 V_fixture_max = 0.000 L_fixture = 0.000H C_fixture = 0.000F | time V(typ) V(min) V(max) Freescale Semiconductor PRELIMINARY 71 Appendix B IBIS Model | 0.000S 0.20nS 0.40nS 0.60nS 0.80nS 1.00nS 1.20nS 1.40nS 1.60nS 1.80nS 2.00nS 2.20nS 2.40nS 2.60nS 2.80nS 3.00nS 3.20nS 3.40nS 3.60nS 3.80nS 4.00nS 4.20nS 4.40nS 4.60nS 4.80nS 5.00nS 5.20nS 5.40nS 5.60nS 5.80nS 6.00nS 6.20nS 6.40nS 6.60nS 6.80nS 7.00nS 7.20nS 7.40nS 7.60nS 7.80nS 8.00nS 8.20nS 8.40nS 1.26uV 1.04uV -5.64uV -0.29mV -3.54mV -3.50mV 33.86mV 79.34mV 0.14V 0.20V 0.28V 0.36V 0.47V 0.60V 0.77V 0.92V 1.03V 1.16V 1.29V 1.39V 1.49V 1.58V 1.65V 1.69V 1.72V 1.76V 1.80V 1.83V 1.86V 1.88V 1.89V 1.91V 1.92V 1.93V 1.94V 1.95V 1.96V 1.97V 1.98V 1.98V 1.98V 1.99V 1.99V 1.62uV 1.45uV -1.36uV -5.13uV 25.94uV -4.79uV -0.86mV -3.75mV -8.09mV 3.52mV 38.97mV 82.84mV 0.13V 0.18V 0.27V 0.34V 0.40V 0.50V 0.59V 0.67V 0.75V 0.84V 0.91V 0.95V 0.99V 1.03V 1.07V 1.12V 1.16V 1.18V 1.20V 1.23V 1.25V 1.27V 1.28V 1.30V 1.31V 1.33V 1.34V 1.35V 1.36V 1.37V 1.37V 1.22uV 0.74uV 11.59uV -3.27mV -9.17mV 56.24mV 0.13V 0.19V 0.27V 0.36V 0.47V 0.59V 0.74V 0.90V 1.12V 1.32V 1.46V 1.63V 1.78V 1.91V 2.01V 2.11V 2.18V 2.21V 2.23V 2.27V 2.29V 2.31V 2.33V 2.34V 2.34V 2.35V 2.36V 2.37V 2.38V 2.38V 2.39V 2.39V 2.39V 2.40V 2.40V 2.40V 2.40V 72 PRELIMINARY Freescale Semiconductor Appendix B IBIS Model 8.60nS 8.80nS 9.00nS 9.20nS 9.40nS 9.60nS 9.80nS 10.00nS | [Rising Waveform] R_fixture = 50.00 V_fixture = 3.30 1.99V 2.00V 2.00V 2.00V 2.01V 2.01V 2.01V 2.01V 1.38V 1.39V 1.39V 1.40V 1.40V 1.41V 1.41V 1.41V 2.41V 2.41V 2.41V 2.41V 2.41V 2.42V 2.42V 2.42V V_fixture_min = 3.00 V_fixture_max = 3.60 L_fixture = 0.000H C_fixture = 0.000F | time | 0.000S 0.20nS 0.40nS 0.60nS 0.80nS 1.00nS 1.20nS 1.40nS 1.60nS 1.80nS 2.00nS 2.20nS 2.40nS 2.60nS 2.80nS 3.00nS 3.20nS 3.40nS 3.60nS 3.80nS 4.00nS 4.20nS 4.40nS 4.60nS 4.80nS 5.00nS 1.27V 1.27V 1.27V 1.27V 1.28V 1.40V 1.60V 1.77V 1.99V 2.24V 2.50V 2.74V 2.94V 3.09V 3.18V 3.24V 3.26V 3.27V 3.29V 3.29V 3.30V 3.30V 3.30V 3.30V 3.30V 3.30V 1.66V 1.66V 1.66V 1.66V 1.66V 1.66V 1.67V 1.69V 1.80V 1.95V 2.13V 2.32V 2.49V 2.63V 2.79V 2.87V 2.91V 2.96V 2.98V 2.99V 2.99V 3.00V 3.00V 3.00V 3.00V 3.00V 1.18V 1.18V 1.18V 1.19V 1.24V 1.47V 1.71V 1.88V 2.12V 2.41V 2.70V 2.99V 3.21V 3.34V 3.44V 3.49V 3.52V 3.55V 3.57V 3.59V 3.59V 3.60V 3.60V 3.60V 3.60V 3.60V V(typ) V(min) V(max) Freescale Semiconductor PRELIMINARY 73 Appendix B IBIS Model 5.20nS 5.40nS 5.60nS 5.80nS 6.00nS 6.20nS 6.40nS 6.60nS 6.80nS 7.00nS 7.20nS 7.40nS 7.60nS 7.80nS 8.00nS 8.20nS 8.40nS 8.60nS 8.80nS 9.00nS 9.20nS 9.40nS 9.60nS 9.80nS 10.00nS | [Falling Waveform] R_fixture = 50.00 V_fixture = 0.000 3.30V 3.30V 3.30V 3.30V 3.30V 3.30V 3.30V 3.30V 3.30V 3.30V 3.30V 3.30V 3.30V 3.30V 3.30V 3.30V 3.30V 3.30V 3.30V 3.30V 3.30V 3.30V 3.30V 3.30V 3.30V 3.00V 3.00V 3.00V 3.00V 3.00V 3.00V 3.00V 3.00V 3.00V 3.00V 3.00V 3.00V 3.00V 3.00V 3.00V 3.00V 3.00V 3.00V 3.00V 3.00V 3.00V 3.00V 3.00V 3.00V 3.00V 3.60V 3.60V 3.60V 3.60V 3.60V 3.60V 3.60V 3.60V 3.60V 3.60V 3.60V 3.60V 3.60V 3.60V 3.60V 3.60V 3.60V 3.60V 3.60V 3.60V 3.60V 3.60V 3.60V 3.60V 3.60V V_fixture_min = 0.000 V_fixture_max = 0.000 L_fixture = 0.000H C_fixture = 0.000F | time | 0.000S 0.20nS 0.40nS 0.60nS 0.80nS 1.00nS 1.20nS 1.40nS 1.60nS 2.02V 2.02V 2.02V 2.02V 1.97V 1.73V 1.45V 1.24V 0.96V 1.44V 1.44V 1.44V 1.44V 1.44V 1.44V 1.42V 1.38V 1.29V 2.43V 2.43V 2.43V 2.38V 2.13V 1.82V 1.49V 1.24V 0.92V V(typ) V(min) V(max) 74 PRELIMINARY Freescale Semiconductor Appendix B IBIS Model 1.80nS 2.00nS 2.20nS 2.40nS 2.60nS 2.80nS 3.00nS 3.20nS 3.40nS 3.60nS 3.80nS 4.00nS 4.20nS 4.40nS 4.60nS 4.80nS 5.00nS 5.20nS 5.40nS 5.60nS 5.80nS 6.00nS 6.20nS 6.40nS 6.60nS 6.80nS 7.00nS 7.20nS 7.40nS 7.60nS 7.80nS 8.00nS 8.20nS 8.40nS 8.60nS 8.80nS 9.00nS 9.20nS 9.40nS 9.60nS 9.80nS 10.00nS | [Falling Waveform] 0.70V 0.50V 0.36V 0.27V 0.20V 0.14V 99.16mV 79.41mV 53.08mV 36.21mV 23.36mV 12.42mV 6.73mV 2.10mV 1.57mV 1.14mV 0.68mV 0.62mV 0.54mV 0.46mV 0.41mV 0.37mV 0.34mV 0.32mV 0.27mV 0.22mV 0.18mV 0.18mV 0.18mV 0.15mV 0.12mV 0.11mV 0.11mV 0.12mV 97.87uV 59.73uV 36.18uV 61.23uV 87.87uV 67.13uV 29.42uV 71.42uV 1.12V 0.92V 0.73V 0.55V 0.40V 0.27V 0.20V 0.16V 0.11V 75.26mV 51.00mV 31.87mV 18.57mV 8.15mV 5.93mV 3.71mV 1.71mV 1.31mV 0.89mV 0.73mV 0.65mV 0.59mV 0.53mV 0.48mV 0.43mV 0.38mV 0.34mV 0.30mV 0.26mV 0.23mV 0.22mV 0.20mV 0.18mV 0.17mV 0.16mV 0.15mV 0.14mV 0.12mV 0.10mV 0.10mV 0.10mV 84.83uV 0.67V 0.50V 0.38V 0.30V 0.24V 0.17V 0.13V 0.11V 78.74mV 59.16mV 39.59mV 27.31mV 15.01mV 7.54mV 4.99mV 2.45mV 1.29mV 0.88mV 0.54mV 0.46mV 0.42mV 0.38mV 0.34mV 0.29mV 0.26mV 0.22mV 0.20mV 0.18mV 0.15mV 0.13mV 0.12mV 0.11mV 0.10mV 92.36uV 78.53uV 64.71uV 61.02uV 60.74uV 58.12uV 46.02uV 39.81uV 50.29uV Freescale Semiconductor PRELIMINARY 75 Appendix B IBIS Model R_fixture = 50.00 V_fixture = 3.30 V_fixture_min = 3.00 V_fixture_max = 3.60 L_fixture = 0.000H C_fixture = 0.000F | time | 0.000S 0.20nS 0.40nS 0.60nS 0.80nS 1.00nS 1.20nS 1.40nS 1.60nS 1.80nS 2.00nS 2.20nS 2.40nS 2.60nS 2.80nS 3.00nS 3.20nS 3.40nS 3.60nS 3.80nS 4.00nS 4.20nS 4.40nS 4.60nS 4.80nS 5.00nS 5.20nS 5.40nS 5.60nS 5.80nS 6.00nS 6.20nS 6.40nS 6.60nS 6.80nS 7.00nS 3.30V 3.30V 3.30V 3.30V 3.30V 3.22V 3.12V 3.06V 2.96V 2.86V 2.75V 2.64V 2.52V 2.40V 2.26V 2.16V 2.10V 2.01V 1.93V 1.86V 1.78V 1.68V 1.58V 1.53V 1.49V 1.43V 1.39V 1.35V 1.32V 1.31V 1.30V 1.29V 1.29V 1.29V 1.28V 1.28V 3.00V 3.00V 3.00V 3.00V 3.00V 3.00V 3.00V 3.00V 3.00V 2.95V 2.89V 2.83V 2.77V 2.70V 2.61V 2.54V 2.48V 2.41V 2.35V 2.30V 2.25V 2.19V 2.13V 2.10V 2.08V 2.04V 2.01V 1.98V 1.95V 1.94V 1.93V 1.91V 1.90V 1.88V 1.87V 1.85V 3.60V 3.60V 3.60V 3.59V 3.48V 3.36V 3.25V 3.16V 3.04V 2.90V 2.76V 2.61V 2.48V 2.34V 2.18V 2.04V 1.93V 1.79V 1.68V 1.57V 1.49V 1.41V 1.34V 1.31V 1.29V 1.26V 1.24V 1.22V 1.21V 1.20V 1.20V 1.19V 1.19V 1.19V 1.19V 1.19V V(typ) V(min) V(max) 76 PRELIMINARY Freescale Semiconductor Appendix B IBIS Model 7.20nS 7.40nS 7.60nS 7.80nS 8.00nS 8.20nS 8.40nS 8.60nS 8.80nS 9.00nS 9.20nS 9.40nS 9.60nS 9.80nS 10.00nS | 1.28V 1.28V 1.28V 1.28V 1.28V 1.28V 1.27V 1.27V 1.27V 1.27V 1.27V 1.27V 1.27V 1.27V 1.27V 1.84V 1.83V 1.82V 1.81V 1.81V 1.80V 1.79V 1.79V 1.78V 1.77V 1.76V 1.75V 1.73V 1.72V 1.71V 1.19V 1.19V 1.19V 1.19V 1.19V 1.19V 1.19V 1.19V 1.19V 1.19V 1.19V 1.19V 1.18V 1.18V 1.18V | End [Model] prd12dgz | |************************************************************************ | | [Model] Model_type Polarity Enable Vinl = Vinh = Vmeas = Cref = Rref = Vref = C_comp | | [Temperature Range] [Pullup Reference] [Pulldown Reference] [POWER Clamp Reference] [GND Clamp Reference] [Pulldown] | voltage | -3.30 -10.00mA 0.000A 0.000A I(typ) I(min) I(max) 25.00 3.30V 0.000V 5.00V 0.000V 0.12k 3.00V 0.000V 4.50V 0.000V 0.000 3.60V 0.000V 5.50V 0.000V 0.80V 2.00V 1.50V 50.00pF 1.00M 0.000V 3.86pF 3.48pF 4.25pF prd16dgz I/O Non-Inverting Active-Low Model prd16dgz |************************************************************************ Freescale Semiconductor PRELIMINARY 77 Appendix B IBIS Model -3.10 -2.90 -2.70 -2.50 -2.30 -2.10 -1.90 -1.70 -1.50 -1.00 -0.90 -0.80 -0.70 -0.60 -0.50 -0.40 -0.30 -0.20 -0.10 -0.00 0.10 0.20 0.30 0.40 0.50 0.60 0.70 0.80 0.90 1.00 1.10 1.20 1.30 1.40 1.50 1.60 1.70 1.80 1.90 2.00 2.10 2.20 2.30 2.40 0.000A 0.000A 0.000A 0.000A 0.000A -10.00mA 0.000A -10.00mA -10.00mA -16.00mA -16.00mA -32.00mA -38.86mA -35.29mA -30.14mA -24.42mA -18.49mA -12.44mA -6.27mA 4.09nA 6.14mA 11.95mA 17.42mA 22.56mA 27.38mA 31.88mA 36.06mA 39.93mA 43.49mA 46.74mA 49.69mA 52.35mA 54.72mA 56.80mA 58.59mA 60.11mA 61.33mA 62.26mA 62.93mA 63.40mA 63.75mA 64.01mA 64.23mA 64.41mA 0.000A 0.000A 0.000A 0.000A 0.000A 0.000A 0.000A 0.000A 0.000A -6.00mA -8.00mA -8.00mA -10.60mA -18.40mA -19.39mA -16.22mA -12.22mA -8.14mA -4.06mA 6.98nA 3.92mA 7.59mA 11.01mA 14.20mA 17.14mA 19.86mA 22.35mA 24.61mA 26.66mA 28.49mA 30.11mA 31.52mA 32.74mA 33.76mA 34.59mA 35.25mA 35.74mA 36.09mA 36.35mA 36.55mA 36.71mA 36.84mA 36.95mA 37.04mA 0.000A 0.000A 0.000A 0.000A 0.000A 0.000A -10.00mA -10.00mA -20.00mA -18.00mA -21.00mA -43.34mA -43.13mA -39.13mA -34.05mA -27.89mA -21.21mA -14.32mA -7.24mA 10.67nA 7.15mA 13.98mA 20.48mA 26.67mA 32.53mA 38.07mA 43.31mA 48.24mA 52.85mA 57.16mA 61.16mA 64.86mA 68.25mA 71.34mA 74.13mA 76.62mA 78.81mA 80.70mA 82.27mA 83.51mA 84.41mA 85.06mA 85.54mA 85.91mA 78 PRELIMINARY Freescale Semiconductor Appendix B IBIS Model 2.50 2.60 2.70 2.80 2.90 3.00 3.10 3.20 3.30 3.40 3.50 3.60 3.70 3.80 3.90 4.00 4.10 4.20 4.30 4.50 4.70 4.90 5.10 5.30 5.50 5.70 5.90 6.10 6.60 | [Pullup] | voltage | -3.30 -3.10 -2.90 -2.70 -2.50 -2.30 -2.10 -1.90 -1.70 -1.50 -1.00 64.56mA 64.70mA 64.82mA 64.94mA 65.04mA 65.14mA 65.23mA 65.32mA 65.40mA 65.49mA 65.59mA 65.66mA 65.75mA 65.86mA 66.08mA 66.86mA 68.11mA 69.36mA 67.34mA 67.43mA 68.10mA 69.00mA 70.20mA 71.67mA 73.47mA 75.61mA 78.09mA 80.89mA 89.06mA 37.13mA 37.21mA 37.28mA 37.34mA 37.40mA 37.46mA 37.51mA 37.57mA 37.63mA 37.81mA 38.34mA 39.10mA 39.94mA 40.42mA 38.09mA 38.16mA 38.25mA 38.35mA 38.47mA 38.78mA 39.19mA 39.73mA 40.44mA 41.32mA 42.38mA 43.64mA 45.10mA 46.75mA 51.59mA 86.20mA 86.45mA 86.66mA 86.85mA 87.02mA 87.17mA 87.32mA 87.45mA 87.58mA 87.70mA 87.82mA 87.93mA 88.05mA 88.16mA 88.29mA 88.44mA 88.63mA 88.90mA 89.46mA 92.67mA 95.47mA 91.91mA 93.29mA 95.00mA 97.12mA 99.69mA 0.10A 0.11A 0.12A I(typ) 0.16A 0.16A 0.15A 0.14A 0.14A 0.13A 0.12A 0.11A 0.10A 93.76mA 70.54mA I(min) 0.12A 0.12A 0.11A 0.11A 0.10A 96.26mA 89.72mA 82.79mA 75.47mA 67.80mA 46.98mA I(max) 0.19A 0.18A 0.17A 0.16A 0.16A 0.15A 0.14A 0.13A 0.12A 0.11A 82.43mA Freescale Semiconductor PRELIMINARY 79 Appendix B IBIS Model -0.90 -0.80 -0.70 -0.60 -0.50 -0.40 -0.30 -0.20 -0.10 0.00 0.10 0.20 0.30 0.40 0.50 0.60 0.70 0.80 0.90 1.00 1.10 1.20 1.30 1.40 1.50 1.60 1.70 1.80 1.90 2.00 2.10 2.20 2.30 2.40 2.50 2.60 2.70 2.80 2.90 3.00 3.10 3.20 3.30 3.40 63.97mA 56.74mA 49.39mA 42.27mA 35.43mA 28.50mA 21.47mA 14.35mA 7.19mA 34.08uA -6.89mA -13.43mA -19.58mA -25.36mA -30.77mA -35.81mA -40.49mA -44.83mA -48.81mA -52.46mA -55.77mA -58.75mA -61.41mA -63.75mA -65.77mA -67.50mA -68.93mA -70.10mA -71.04mA -71.82mA -72.46mA -73.01mA -73.48mA -73.90mA -74.27mA -74.60mA -74.91mA -75.18mA -75.44mA -75.68mA -75.90mA -76.12mA -76.32mA -76.52mA 42.83mA 41.47mA 36.27mA 30.78mA 25.27mA 19.90mA 14.79mA 9.79mA 4.85mA 11.19uA -4.62mA -8.98mA -13.08mA -16.92mA -20.50mA -23.82mA -26.89mA -29.70mA -32.27mA -34.60mA -36.68mA -38.52mA -40.13mA -41.50mA -42.65mA -43.58mA -44.31mA -44.87mA -45.31mA -45.68mA -46.00mA -46.28mA -46.53mA -46.76mA -46.97mA -47.17mA -47.35mA -47.52mA -47.68mA -47.83mA -47.97mA -48.11mA -48.27mA -48.87mA 74.23mA 65.83mA 57.50mA 49.67mA 41.79mA 33.74mA 25.52mA 17.14mA 8.64mA 71.92uA -8.29mA -16.24mA -23.77mA -30.88mA -37.60mA -43.93mA -49.86mA -55.41mA -60.59mA -65.39mA -69.83mA -73.91mA -77.64mA -81.02mA -84.06mA -86.77mA -89.14mA -91.20mA -92.94mA -94.40mA -95.60mA -96.60mA -97.44mA -98.15mA -98.77mA -99.31mA -99.80mA -0.10A -0.10A -0.10A -0.10A -0.10A -0.10A -0.10A 80 PRELIMINARY Freescale Semiconductor Appendix B IBIS Model 3.50 3.60 3.70 3.80 3.90 4.00 4.10 4.20 4.30 4.50 4.70 4.90 5.10 5.30 5.50 5.70 5.90 6.10 6.60 | [GND_clamp] | voltage | -5.00 -4.80 -4.60 -4.40 -4.20 -4.00 -3.80 -3.60 -3.40 -3.20 -3.00 -2.80 -2.60 -2.40 -2.20 -2.00 -1.80 -1.60 -1.40 -1.20 -1.00 -76.71mA -76.89mA -77.09mA -77.56mA -79.54mA -90.56mA -0.31A -1.88A -3.93A -8.04A -12.14A -16.25A -20.36A -24.46A -28.57A -32.68A -36.78A -40.89A -51.16A -56.48mA -0.15A -0.95A -2.71A -4.50A -6.29A -8.09A -9.88A -11.66A -15.24A -18.83A -22.41A -25.99A -29.57A -33.15A -36.73A -40.31A -43.89A -52.84A -0.10A -0.10A -0.10A -0.10A -0.10A -0.10A -0.11A -0.11A -0.12A -1.17A -5.43A -9.69A -13.95A -18.21A -22.48A -26.74A -31.00A -35.27A -45.93A I(typ) -85.90A -81.80A -77.70A -73.60A -69.50A -65.40A -61.30A -57.20A -53.10A -49.00A -44.90A -40.80A -36.69A -32.59A -28.49A -24.38A -20.28A -16.17A -12.06A -7.96A -3.86A I(min) -77.84A -74.26A -70.68A -67.10A -63.52A -59.94A -56.36A -52.78A -49.20A -45.62A -42.04A -38.46A -34.89A -31.31A -27.73A -24.15A -20.57A -16.99A -13.40A -9.83A -6.25A I(max) -88.40A -84.14A -79.88A -75.62A -71.36A -67.10A -62.84A -58.58A -54.32A -50.06A -45.80A -41.54A -37.28A -33.02A -28.76A -24.50A -20.24A -15.97A -11.71A -7.45A -3.19A Freescale Semiconductor PRELIMINARY 81 Appendix B IBIS Model -0.80 -0.60 -0.40 -0.20 -0.00 0.20 0.40 0.60 0.80 1.00 1.20 1.40 1.60 1.80 2.00 2.20 2.40 2.60 2.80 3.00 3.20 3.40 3.60 3.80 4.00 4.20 4.40 4.60 4.80 5.00 | [POWER_clamp] | voltage | -5.00 -4.90 -4.80 -4.70 -4.60 -4.50 -4.40 -4.30 -4.20 -4.10 -0.23A -2.22mA -89.20uA -27.89uA -62.88nA 18.73uA 29.21uA 32.51uA 33.09uA 33.31uA 33.46uA 33.58uA 33.69uA 33.78uA 33.87uA 33.96uA 34.01uA 34.03uA 34.04uA 34.05uA 34.06uA 34.08uA 34.10uA 34.12uA 34.14uA 34.16uA 34.18uA 34.20uA 34.22uA 34.24uA -2.66A -0.10A -0.52mA -14.67uA -63.80nA 7.33uA 10.27uA 10.69uA 10.80uA 10.87uA 10.93uA 10.98uA 11.03uA 11.08uA 11.12uA 11.14uA 11.15uA 11.16uA 11.17uA 11.18uA 11.57uA 10.87uA 10.17uA 9.47uA 8.77uA 8.07uA 7.37uA 6.67uA 5.97uA 5.27uA -70.76mA -5.90mA -0.26mA -42.88uA -74.38nA 32.30uA 54.14uA 65.81uA 69.35uA 70.19uA 70.56uA 70.81uA 71.00uA 71.17uA 71.33uA 71.47uA 71.62uA 71.76uA 71.84uA 71.86uA 71.88uA 71.90uA 71.92uA 71.94uA 71.96uA 71.98uA 72.00uA 72.02uA 72.04uA 72.06uA I(typ) 48.54uA 48.21uA 47.88uA 47.55uA 47.22uA 46.89uA 46.56uA 46.23uA 45.90uA 45.57uA I(min) 16.29uA 16.17uA 16.05uA 15.93uA 15.81uA 15.69uA 15.57uA 15.45uA 15.33uA 15.21uA I(max) 95.93uA 95.42uA 94.91uA 94.40uA 93.89uA 93.38uA 92.87uA 92.36uA 91.85uA 91.34uA 82 PRELIMINARY Freescale Semiconductor Appendix B IBIS Model -4.00 -3.90 -3.80 -3.70 -3.60 -3.50 -3.40 -3.30 -3.20 -3.10 -3.00 -2.90 -2.80 -2.70 -2.60 -2.50 -2.40 -2.30 -2.20 -2.10 -2.00 -1.90 -1.80 -1.70 -1.60 -1.50 -1.40 -1.30 -1.20 -1.10 -1.00 -0.90 -0.80 -0.70 -0.60 -0.50 -0.40 -0.30 -0.20 -0.10 0.00 | [Ramp] | variable 45.24uA 44.91uA 44.58uA 44.25uA 43.92uA 43.59uA 43.26uA 42.93uA 42.60uA 42.27uA 41.94uA 41.61uA 41.28uA 40.95uA 40.62uA 40.29uA 39.96uA 39.63uA 39.30uA 38.97uA 38.64uA 38.31uA 37.98uA 37.65uA 37.32uA 36.99uA 36.68uA 36.39uA 36.12uA 35.87uA 35.63uA 35.42uA 35.23uA 35.06uA 34.91uA 34.78uA 34.66uA 34.56uA 34.48uA 34.41uA 34.35uA 15.09uA 14.97uA 14.85uA 14.73uA 14.61uA 14.49uA 14.37uA 14.25uA 14.13uA 14.01uA 13.89uA 13.77uA 13.65uA 13.53uA 13.41uA 13.29uA 13.17uA 13.05uA 12.93uA 12.81uA 12.69uA 12.57uA 12.45uA 12.33uA 12.22uA 12.11uA 12.02uA 11.92uA 11.84uA 11.76uA 11.69uA 11.63uA 11.58uA 11.53uA 11.48uA 11.44uA 11.41uA 11.38uA 11.36uA 11.34uA 11.32uA 90.83uA 90.32uA 89.81uA 89.30uA 88.79uA 88.28uA 87.77uA 87.26uA 86.75uA 86.24uA 85.73uA 85.22uA 84.71uA 84.20uA 83.69uA 83.18uA 82.67uA 82.16uA 81.65uA 81.14uA 80.63uA 80.12uA 79.61uA 79.10uA 78.59uA 78.08uA 77.57uA 77.06uA 76.55uA 76.04uA 75.53uA 75.06uA 74.64uA 74.25uA 73.90uA 73.58uA 73.31uA 73.07uA 72.87uA 72.69uA 72.55uA typ min max Freescale Semiconductor PRELIMINARY 83 Appendix B IBIS Model dV/dt_r dV/dt_f R_load = 50.00 | [Rising Waveform] R_fixture = 50.00 V_fixture = 0.000 1.43/2.06n 1.39/2.80n 1.08/2.82n 0.98/4.41n 1.66/1.86n 1.61/2.52n V_fixture_min = 0.000 V_fixture_max = 0.000 L_fixture = 0.000H C_fixture = 0.000F | time | 0.000S 0.20nS 0.40nS 0.60nS 0.80nS 1.00nS 1.20nS 1.40nS 1.60nS 1.80nS 2.00nS 2.20nS 2.40nS 2.60nS 2.80nS 3.00nS 3.20nS 3.40nS 3.60nS 3.80nS 4.00nS 4.20nS 4.40nS 4.60nS 4.80nS 5.00nS 5.20nS 5.40nS 5.60nS 5.80nS 6.00nS 0.71uV 0.48uV -6.07uV -0.29mV -3.39mV -4.34mV 25.79mV 62.40mV 0.11V 0.16V 0.22V 0.28V 0.37V 0.48V 0.63V 0.79V 0.90V 1.07V 1.24V 1.39V 1.55V 1.71V 1.84V 1.90V 1.96V 2.03V 2.08V 2.13V 2.18V 2.20V 2.22V 0.94uV 0.81uV -1.89uV -5.66uV 26.90uV -5.17uV -0.87mV -3.65mV -7.89mV 0.71mV 29.71mV 65.63mV 0.10V 0.15V 0.22V 0.28V 0.34V 0.43V 0.53V 0.63V 0.74V 0.86V 0.97V 1.03V 1.09V 1.16V 1.22V 1.29V 1.36V 1.39V 1.43V 0.68uV 0.000V 12.38uV -3.13mV -6.39mV 43.34mV 0.11V 0.15V 0.21V 0.28V 0.37V 0.46V 0.59V 0.71V 0.92V 1.12V 1.28V 1.49V 1.70V 1.89V 2.07V 2.24V 2.37V 2.44V 2.50V 2.54V 2.59V 2.62V 2.65V 2.66V 2.67V V(typ) V(min) V(max) 84 PRELIMINARY Freescale Semiconductor Appendix B IBIS Model 6.20nS 6.40nS 6.60nS 6.80nS 7.00nS 7.20nS 7.40nS 7.60nS 7.80nS 8.00nS 8.20nS 8.40nS 8.60nS 8.80nS 9.00nS 9.20nS 9.40nS 9.60nS 9.80nS 10.00nS | [Rising Waveform] R_fixture = 50.00 V_fixture = 3.30 2.24V 2.26V 2.27V 2.29V 2.30V 2.31V 2.32V 2.33V 2.34V 2.34V 2.35V 2.35V 2.36V 2.36V 2.36V 2.37V 2.37V 2.38V 2.38V 2.38V 1.47V 1.51V 1.54V 1.57V 1.60V 1.63V 1.66V 1.68V 1.69V 1.70V 1.72V 1.73V 1.74V 1.75V 1.76V 1.77V 1.78V 1.79V 1.80V 1.80V 2.68V 2.69V 2.70V 2.71V 2.72V 2.72V 2.73V 2.74V 2.74V 2.74V 2.75V 2.75V 2.75V 2.76V 2.76V 2.76V 2.76V 2.77V 2.77V 2.77V V_fixture_min = 3.00 V_fixture_max = 3.60 L_fixture = 0.000H C_fixture = 0.000F | time | 0.000S 0.20nS 0.40nS 0.60nS 0.80nS 1.00nS 1.20nS 1.40nS 1.60nS 1.80nS 2.00nS 2.20nS 2.40nS 2.60nS 0.98V 0.98V 0.98V 0.98V 0.99V 1.05V 1.18V 1.31V 1.49V 1.69V 1.92V 2.18V 2.46V 2.73V 1.34V 1.34V 1.34V 1.34V 1.34V 1.34V 1.34V 1.36V 1.44V 1.57V 1.73V 1.92V 2.11V 2.32V 0.92V 0.92V 0.92V 0.92V 0.94V 1.07V 1.24V 1.37V 1.55V 1.76V 2.02V 2.33V 2.62V 2.91V V(typ) V(min) V(max) Freescale Semiconductor PRELIMINARY 85 Appendix B IBIS Model 2.80nS 3.00nS 3.20nS 3.40nS 3.60nS 3.80nS 4.00nS 4.20nS 4.40nS 4.60nS 4.80nS 5.00nS 5.20nS 5.40nS 5.60nS 5.80nS 6.00nS 6.20nS 6.40nS 6.60nS 6.80nS 7.00nS 7.20nS 7.40nS 7.60nS 7.80nS 8.00nS 8.20nS 8.40nS 8.60nS 8.80nS 9.00nS 9.20nS 9.40nS 9.60nS 9.80nS 10.00nS | [Falling Waveform] R_fixture = 50.00 V_fixture = 0.000 2.97V 3.09V 3.15V 3.20V 3.24V 3.26V 3.28V 3.29V 3.29V 3.30V 3.30V 3.30V 3.30V 3.30V 3.30V 3.30V 3.30V 3.30V 3.30V 3.30V 3.30V 3.30V 3.30V 3.30V 3.30V 3.30V 3.30V 3.30V 3.30V 3.30V 3.30V 3.30V 3.30V 3.30V 3.30V 3.30V 3.30V 2.55V 2.69V 2.76V 2.86V 2.92V 2.95V 2.98V 2.99V 2.99V 3.00V 3.00V 3.00V 3.00V 3.00V 3.00V 3.00V 3.00V 3.00V 3.00V 3.00V 3.00V 3.00V 3.00V 3.00V 3.00V 3.00V 3.00V 3.00V 3.00V 3.00V 3.00V 3.00V 3.00V 3.00V 3.00V 3.00V 3.00V 3.20V 3.33V 3.39V 3.44V 3.50V 3.53V 3.55V 3.57V 3.59V 3.59V 3.59V 3.60V 3.60V 3.60V 3.60V 3.60V 3.60V 3.60V 3.60V 3.60V 3.60V 3.60V 3.60V 3.60V 3.60V 3.60V 3.60V 3.60V 3.60V 3.60V 3.60V 3.60V 3.60V 3.60V 3.60V 3.60V 3.60V V_fixture_min = 0.000 V_fixture_max = 0.000 L_fixture = 0.000H 86 PRELIMINARY Freescale Semiconductor Appendix B IBIS Model C_fixture = 0.000F | time | 0.000S 0.20nS 0.40nS 0.60nS 0.80nS 1.00nS 1.20nS 1.40nS 1.60nS 1.80nS 2.00nS 2.20nS 2.40nS 2.60nS 2.80nS 3.00nS 3.20nS 3.40nS 3.60nS 3.80nS 4.00nS 4.20nS 4.40nS 4.60nS 4.80nS 5.00nS 5.20nS 5.40nS 5.60nS 5.80nS 6.00nS 6.20nS 6.40nS 6.60nS 6.80nS 7.00nS 7.20nS 7.40nS 7.60nS 7.80nS 8.00nS 2.41V 2.41V 2.41V 2.41V 2.37V 2.24V 2.07V 1.94V 1.76V 1.54V 1.28V 1.01V 0.78V 0.61V 0.46V 0.37V 0.33V 0.26V 0.21V 0.17V 0.14V 0.10V 73.29mV 60.19mV 48.89mV 34.23mV 24.65mV 14.47mV 8.10mV 5.49mV 3.06mV 1.82mV 1.09mV 0.61mV 0.54mV 0.47mV 0.42mV 0.35mV 0.31mV 0.29mV 0.27mV 1.87V 1.87V 1.87V 1.87V 1.87V 1.86V 1.85V 1.82V 1.75V 1.65V 1.51V 1.36V 1.18V 0.99V 0.76V 0.59V 0.49V 0.39V 0.31V 0.25V 0.19V 0.15V 0.10V 87.46mV 70.67mV 50.83mV 38.23mV 23.57mV 14.65mV 9.93mV 6.30mV 4.27mV 2.24mV 1.46mV 1.08mV 0.78mV 0.69mV 0.59mV 0.52mV 0.48mV 0.45mV 2.79V 2.79V 2.79V 2.76V 2.62V 2.44V 2.25V 2.10V 1.85V 1.55V 1.23V 0.96V 0.77V 0.63V 0.51V 0.43V 0.37V 0.32V 0.27V 0.22V 0.19V 0.14V 0.11V 93.57mV 78.29mV 61.98mV 46.06mV 32.51mV 20.47mV 15.65mV 11.70mV 6.64mV 4.15mV 2.31mV 1.05mV 0.76mV 0.48mV 0.37mV 0.31mV 0.29mV 0.26mV V(typ) V(min) V(max) Freescale Semiconductor PRELIMINARY 87 Appendix B IBIS Model 8.20nS 8.40nS 8.60nS 8.80nS 9.00nS 9.20nS 9.40nS 9.60nS 9.80nS 10.00nS | [Falling Waveform] R_fixture = 50.00 V_fixture = 3.30 0.24mV 0.20mV 0.18mV 0.18mV 0.17mV 0.15mV 0.12mV 0.10mV 0.11mV 0.11mV 0.40mV 0.35mV 0.32mV 0.31mV 0.28mV 0.24mV 0.20mV 0.19mV 0.20mV 0.17mV 0.24mV 0.21mV 0.18mV 0.16mV 0.16mV 0.15mV 0.12mV 93.74uV 90.71uV 97.83uV V_fixture_min = 3.00 V_fixture_max = 3.60 L_fixture = 0.000H C_fixture = 0.000F | time | 0.000S 0.20nS 0.40nS 0.60nS 0.80nS 1.00nS 1.20nS 1.40nS 1.60nS 1.80nS 2.00nS 2.20nS 2.40nS 2.60nS 2.80nS 3.00nS 3.20nS 3.40nS 3.60nS 3.80nS 4.00nS 4.20nS 4.40nS 4.60nS 3.30V 3.30V 3.30V 3.30V 3.30V 3.25V 3.17V 3.12V 3.05V 2.97V 2.87V 2.78V 2.68V 2.58V 2.45V 2.34V 2.26V 2.17V 2.07V 1.98V 1.89V 1.76V 1.63V 1.55V 3.00V 3.00V 3.00V 3.00V 3.00V 3.00V 3.00V 3.00V 3.00V 2.97V 2.92V 2.87V 2.82V 2.76V 2.69V 2.62V 2.57V 2.50V 2.44V 2.38V 2.32V 2.25V 2.18V 2.15V 3.60V 3.60V 3.60V 3.59V 3.52V 3.43V 3.34V 3.27V 3.17V 3.06V 2.95V 2.83V 2.70V 2.58V 2.43V 2.30V 2.21V 2.07V 1.91V 1.76V 1.62V 1.49V 1.37V 1.32V V(typ) V(min) V(max) 88 PRELIMINARY Freescale Semiconductor Appendix B IBIS Model 4.80nS 5.00nS 5.20nS 5.40nS 5.60nS 5.80nS 6.00nS 6.20nS 6.40nS 6.60nS 6.80nS 7.00nS 7.20nS 7.40nS 7.60nS 7.80nS 8.00nS 8.20nS 8.40nS 8.60nS 8.80nS 9.00nS 9.20nS 9.40nS 9.60nS 9.80nS 10.00nS | 1.48V 1.40V 1.32V 1.25V 1.19V 1.15V 1.13V 1.10V 1.07V 1.05V 1.03V 1.02V 1.01V 1.00V 1.00V 1.00V 1.00V 0.99V 0.99V 0.99V 0.99V 0.99V 0.99V 0.99V 0.99V 0.99V 0.99V 2.11V 2.06V 2.01V 1.96V 1.92V 1.89V 1.87V 1.84V 1.81V 1.78V 1.75V 1.72V 1.70V 1.67V 1.64V 1.62V 1.60V 1.57V 1.53V 1.50V 1.47V 1.44V 1.42V 1.40V 1.38V 1.37V 1.36V 1.27V 1.21V 1.16V 1.10V 1.06V 1.04V 1.02V 1.00V 0.98V 0.96V 0.95V 0.94V 0.93V 0.93V 0.92V 0.92V 0.92V 0.92V 0.92V 0.92V 0.92V 0.92V 0.92V 0.92V 0.92V 0.92V 0.92V | End [Model] prd16dgz | |************************************************************************ | | [Model] Model_type Polarity Enable Vinl = Vinh = Vmeas = Cref = Rref = Vref = 0.80V 2.00V 1.50V 50.00pF 1.00M 0.000V prd24dgz I/O Non-Inverting Active-Low Model prd24dgz |************************************************************************ Freescale Semiconductor PRELIMINARY 89 Appendix B IBIS Model C_comp | | 4.15pF 3.73pF 4.56pF [Temperature Range] [Pullup Reference] [Pulldown Reference] [POWER Clamp Reference] [GND Clamp Reference] [Pulldown] | voltage | -3.30 -3.10 -2.90 -2.70 -2.50 -2.30 -2.10 -1.90 -1.70 -1.50 -1.00 -0.90 -0.80 -0.70 -0.60 -0.50 -0.40 -0.30 -0.20 -0.10 -0.00 0.10 0.20 0.30 0.40 0.50 0.60 0.70 0.80 0.90 1.00 1.10 1.20 -10.00mA 0.000A 0.000A 0.000A 0.000A 0.000A -10.00mA -10.00mA -10.00mA -10.00mA -19.00mA -21.00mA -41.70mA -50.61mA -46.07mA -39.45mA -32.03mA -24.29mA -16.36mA -8.26mA 3.80nA 8.11mA 15.76mA 22.98mA 29.76mA 36.11mA 42.04mA 47.55mA 52.66mA 57.35mA 61.65mA 65.55mA 69.06mA I(typ) 25.00 3.30V 0.000V 5.00V 0.000V I(min) 0.000A 0.000A 0.000A 0.000A 0.000A 0.000A 0.000A 0.000A -10.00mA -10.00mA -10.00mA -10.00mA -11.00mA -14.60mA -25.10mA -26.37mA -22.06mA -16.63mA -11.11mA -5.55mA 7.33nA 5.36mA 10.37mA 15.05mA 19.40mA 23.42mA 27.12mA 30.50mA 33.58mA 36.36mA 38.84mA 41.04mA 42.96mA 0.12k 3.00V 0.000V 4.50V 0.000V I(max) 0.000A -10.00mA 0.000A 0.000A 0.000A -10.00mA -10.00mA -10.00mA -10.00mA -20.00mA -23.00mA -26.00mA -55.33mA -55.12mA -50.21mA -43.90mA -36.08mA -27.48mA -18.57mA -9.40mA 12.06nA 9.30mA 18.18mA 26.64mA 34.69mA 42.32mA 49.54mA 56.36mA 62.78mA 68.80mA 74.42mA 79.65mA 84.48mA 0.000 3.60V 0.000V 5.50V 0.000V 90 PRELIMINARY Freescale Semiconductor Appendix B IBIS Model 1.30 1.40 1.50 1.60 1.70 1.80 1.90 2.00 2.10 2.20 2.30 2.40 2.50 2.60 2.70 2.80 2.90 3.00 3.10 3.20 3.30 3.40 3.50 3.60 3.70 3.80 3.90 4.00 4.10 4.20 4.30 4.50 4.70 4.90 5.10 5.30 5.50 5.70 5.90 6.10 6.60 | [Pullup] | voltage 72.19mA 74.94mA 77.32mA 79.33mA 80.95mA 82.19mA 83.09mA 83.74mA 84.23mA 84.62mA 84.93mA 85.20mA 85.44mA 85.65mA 85.84mA 86.01mA 86.18mA 86.33mA 86.48mA 86.62mA 86.75mA 86.89mA 87.06mA 87.16mA 87.30mA 87.47mA 87.77mA 88.66mA 90.00mA 91.34mA 89.39mA 89.66mA 90.64mA 91.94mA 93.66mA 95.77mA 98.33mA 0.10A 0.10A 0.11A 0.12A 44.61mA 45.99mA 47.12mA 48.01mA 48.68mA 49.17mA 49.54mA 49.83mA 50.06mA 50.25mA 50.42mA 50.57mA 50.70mA 50.82mA 50.93mA 51.03mA 51.13mA 51.22mA 51.31mA 51.40mA 51.50mA 51.73mA 52.32mA 53.14mA 54.02mA 54.48mA 52.16mA 52.28mA 52.42mA 52.58mA 52.77mA 53.24mA 53.86mA 54.68mA 55.73mA 57.03mA 58.59mA 60.44mA 62.55mA 64.93mA 71.83mA 88.92mA 92.97mA 96.63mA 99.91mA 0.10A 0.11A 0.11A 0.11A 0.11A 0.11A 0.11A 0.11A 0.11A 0.11A 0.11A 0.11A 0.11A 0.11A 0.11A 0.11A 0.11A 0.12A 0.12A 0.12A 0.12A 0.12A 0.12A 0.12A 0.12A 0.12A 0.12A 0.12A 0.12A 0.12A 0.12A 0.13A 0.13A 0.13A 0.14A 0.14A 0.15A I(typ) I(min) I(max) Freescale Semiconductor PRELIMINARY 91 Appendix B IBIS Model | -3.30 -3.10 -2.90 -2.70 -2.50 -2.30 -2.10 -1.90 -1.70 -1.50 -1.00 -0.90 -0.80 -0.70 -0.60 -0.50 -0.40 -0.30 -0.20 -0.10 0.00 0.10 0.20 0.30 0.40 0.50 0.60 0.70 0.80 0.90 1.00 1.10 1.20 1.30 1.40 1.50 1.60 1.70 1.80 1.90 2.00 2.10 2.20 0.22A 0.21A 0.20A 0.19A 0.18A 0.17A 0.16A 0.15A 0.14A 0.12A 92.80mA 84.30mA 75.06mA 65.63mA 56.31mA 47.22mA 38.00mA 28.62mA 19.12mA 9.57mA 34.08uA -9.20mA -17.92mA -26.12mA -33.83mA -41.04mA -47.76mA -54.01mA -59.78mA -65.10mA -69.96mA -74.37mA -78.35mA -81.89mA -85.01mA -87.72mA -90.01mA -91.93mA -93.48mA -94.74mA -95.77mA -96.63mA -97.36mA 0.16A 0.16A 0.15A 0.14A 0.14A 0.13A 0.12A 0.11A 0.10A 90.15mA 62.50mA 57.02mA 54.41mA 47.70mA 40.65mA 33.53mA 26.51mA 19.71mA 13.04mA 6.46mA 11.19uA -6.16mA -11.98mA -17.45mA -22.56mA -27.33mA -31.76mA -35.85mA -39.61mA -43.04mA -46.14mA -48.91mA -51.37mA -53.51mA -55.34mA -56.87mA -58.11mA -59.08mA -59.83mA -60.42mA -60.91mA -61.34mA -61.71mA 0.25A 0.24A 0.23A 0.22A 0.21A 0.20A 0.19A 0.17A 0.16A 0.14A 0.11A 97.94mA 87.24mA 76.50mA 66.14mA 55.68mA 44.96mA 34.00mA 22.83mA 11.50mA 71.92uA -11.08mA -21.68mA -31.71mA -41.21mA -50.17mA -58.60mA -66.51mA -73.91mA -80.81mA -87.22mA -93.14mA -98.58mA -0.10A -0.11A -0.11A -0.12A -0.12A -0.12A -0.12A -0.13A -0.13A -0.13A 92 PRELIMINARY Freescale Semiconductor Appendix B IBIS Model 2.30 2.40 2.50 2.60 2.70 2.80 2.90 3.00 3.10 3.20 3.30 3.40 3.50 3.60 3.70 3.80 3.90 4.00 4.10 4.20 4.30 4.50 4.70 4.90 5.10 5.30 5.50 5.70 5.90 6.10 6.60 | [GND_clamp] | voltage | -5.00 -4.80 -4.60 -4.40 -4.20 -4.00 -3.80 -3.60 -3.40 -97.99mA -98.55mA -99.04mA -99.49mA -99.89mA -0.10A -0.10A -0.10A -0.10A -0.10A -0.10A -0.10A -0.10A -0.10A -0.10A -0.10A -0.11A -0.12A -0.34A -1.90A -3.94A -8.02A -12.10A -16.18A -20.27A -24.35A -28.43A -32.51A -36.60A -40.68A -50.89A -62.05mA -62.36mA -62.64mA -62.90mA -63.14mA -63.36mA -63.57mA -63.78mA -63.97mA -64.15mA -64.35mA -64.99mA -72.69mA -0.17A -0.97A -2.72A -4.50A -6.28A -8.06A -9.85A -11.62A -15.19A -18.75A -22.31A -25.88A -29.44A -33.00A -36.56A -40.13A -43.69A -52.59A -0.13A -0.13A -0.13A -0.13A -0.13A -0.13A -0.13A -0.13A -0.14A -0.14A -0.14A -0.14A -0.14A -0.14A -0.14A -0.14A -0.14A -0.14A -0.14A -0.14A -0.15A -1.21A -5.43A -9.67A -13.90A -18.14A -22.38A -26.62A -30.86A -35.09A -45.69A I(typ) -85.26A -81.20A -77.14A -73.08A -69.02A -64.96A -60.90A -56.84A -52.78A I(min) -77.43A -73.87A -70.31A -66.75A -63.19A -59.63A -56.07A -52.51A -48.95A I(max) -87.91A -83.67A -79.43A -75.19A -70.95A -66.71A -62.47A -58.23A -53.99A Freescale Semiconductor PRELIMINARY 93 Appendix B IBIS Model -3.20 -3.00 -2.80 -2.60 -2.40 -2.20 -2.00 -1.80 -1.60 -1.40 -1.20 -1.00 -0.80 -0.60 -0.40 -0.20 -0.00 0.20 0.40 0.60 0.80 1.00 1.20 1.40 1.60 1.80 2.00 2.20 2.40 2.60 2.80 3.00 3.20 3.40 3.60 3.80 4.00 4.20 4.40 4.60 4.80 5.00 | [POWER_clamp] -48.72A -44.64A -40.56A -36.48A -32.40A -28.32A -24.24A -20.16A -16.08A -12.00A -7.92A -3.84A -0.23A -2.33mA -91.55uA -27.91uA -75.80nA 18.72uA 29.20uA 32.50uA 33.08uA 33.30uA 33.45uA 33.57uA 33.68uA 33.78uA 33.87uA 33.96uA 34.01uA 34.03uA 34.04uA 34.05uA 34.06uA 34.08uA 34.10uA 34.12uA 34.14uA 34.16uA 34.18uA 34.20uA 34.22uA 34.24uA -45.39A -41.83A -38.27A -34.71A -31.15A -27.59A -24.03A -20.47A -16.90A -13.34A -9.78A -6.22A -2.66A -0.10A -0.52mA -14.70uA -77.03nA 7.32uA 10.26uA 10.68uA 10.79uA 10.86uA 10.92uA 10.98uA 11.03uA 11.07uA 11.11uA 11.14uA 11.15uA 11.16uA 11.17uA 11.18uA 11.75uA 10.69uA 9.63uA 8.57uA 7.51uA 6.45uA 5.39uA 4.33uA 3.27uA 2.21uA -49.75A -45.52A -41.29A -37.05A -32.82A -28.58A -24.35A -20.11A -15.88A -11.64A -7.41A -3.18A -71.67mA -6.23mA -0.28mA -42.94uA -90.19nA 32.29uA 54.13uA 65.79uA 69.34uA 70.18uA 70.55uA 70.80uA 71.00uA 71.16uA 71.32uA 71.47uA 71.61uA 71.76uA 71.84uA 71.86uA 71.88uA 71.90uA 71.92uA 71.94uA 71.96uA 71.98uA 72.00uA 72.02uA 72.04uA 72.06uA 94 PRELIMINARY Freescale Semiconductor Appendix B IBIS Model | voltage | -5.00 -4.90 -4.80 -4.70 -4.60 -4.50 -4.40 -4.30 -4.20 -4.10 -4.00 -3.90 -3.80 -3.70 -3.60 -3.50 -3.40 -3.30 -3.20 -3.10 -3.00 -2.90 -2.80 -2.70 -2.60 -2.50 -2.40 -2.30 -2.20 -2.10 -2.00 -1.90 -1.80 -1.70 -1.60 -1.50 -1.40 -1.30 -1.20 -1.10 -1.00 -0.90 I(typ) 48.55uA 48.22uA 47.89uA 47.56uA 47.23uA 46.90uA 46.57uA 46.24uA 45.91uA 45.58uA 45.25uA 44.92uA 44.59uA 44.26uA 43.93uA 43.60uA 43.27uA 42.94uA 42.61uA 42.28uA 41.95uA 41.62uA 41.29uA 40.96uA 40.63uA 40.30uA 39.97uA 39.64uA 39.31uA 38.98uA 38.65uA 38.32uA 37.99uA 37.66uA 37.33uA 37.00uA 36.69uA 36.40uA 36.13uA 35.88uA 35.64uA 35.43uA I(min) 16.31uA 16.19uA 16.07uA 15.95uA 15.83uA 15.71uA 15.59uA 15.47uA 15.35uA 15.23uA 15.11uA 14.99uA 14.87uA 14.75uA 14.63uA 14.51uA 14.39uA 14.27uA 14.15uA 14.03uA 13.91uA 13.79uA 13.67uA 13.55uA 13.43uA 13.31uA 13.19uA 13.07uA 12.95uA 12.83uA 12.71uA 12.59uA 12.47uA 12.35uA 12.23uA 12.13uA 12.03uA 11.94uA 11.85uA 11.78uA 11.71uA 11.64uA I(max) 95.55uA 95.05uA 94.55uA 94.05uA 93.55uA 93.05uA 92.55uA 92.05uA 91.55uA 91.05uA 90.55uA 90.05uA 89.55uA 89.05uA 88.55uA 88.05uA 87.55uA 87.05uA 86.55uA 86.05uA 85.55uA 85.05uA 84.55uA 84.05uA 83.55uA 83.05uA 82.55uA 82.05uA 81.55uA 81.05uA 80.55uA 80.05uA 79.55uA 79.05uA 78.55uA 78.05uA 77.55uA 77.05uA 76.55uA 76.05uA 75.55uA 75.08uA Freescale Semiconductor PRELIMINARY 95 Appendix B IBIS Model -0.80 -0.70 -0.60 -0.50 -0.40 -0.30 -0.20 -0.10 0.00 | [Ramp] | variable dV/dt_r dV/dt_f R_load = 50.00 | 35.24uA 35.07uA 34.92uA 34.79uA 34.67uA 34.57uA 34.49uA 34.42uA 34.36uA 11.59uA 11.54uA 11.49uA 11.45uA 11.42uA 11.39uA 11.37uA 11.35uA 11.33uA 74.65uA 74.26uA 73.91uA 73.60uA 73.32uA 73.08uA 72.88uA 72.70uA 72.56uA typ 1.54/2.22n 1.52/3.16n min 1.20/2.88n 1.15/4.46n max 1.77/2.15n 1.73/3.00n [Rising Waveform] R_fixture = 50.00 V_fixture = 0.000 V_fixture_min = 0.000 V_fixture_max = 0.000 L_fixture = 0.000H C_fixture = 0.000F | time | 0.000S 0.20nS 0.40nS 0.60nS 0.80nS 1.00nS 1.20nS 1.40nS 1.60nS 1.80nS 2.00nS 2.20nS 2.40nS 2.60nS 2.80nS 3.00nS 3.20nS 3.40nS 3.60nS 0.70uV 0.45uV -5.49uV -0.25mV -2.88mV -3.85mV 18.80mV 45.63mV 80.05mV 0.11V 0.16V 0.20V 0.26V 0.32V 0.41V 0.51V 0.58V 0.71V 0.85V 0.92uV 0.77uV -1.76uV -4.97uV 24.27uV -5.54uV -0.76mV -3.09mV -6.58mV -0.18mV 21.52mV 48.21mV 76.15mV 0.11V 0.16V 0.19V 0.24V 0.30V 0.36V 0.68uV 0.000V 16.07uV -2.66mV -5.55mV 32.40mV 80.52mV 0.11V 0.16V 0.21V 0.27V 0.33V 0.41V 0.48V 0.61V 0.73V 0.82V 0.97V 1.16V V(typ) V(min) V(max) 96 PRELIMINARY Freescale Semiconductor Appendix B IBIS Model 3.80nS 4.00nS 4.20nS 4.40nS 4.60nS 4.80nS 5.00nS 5.20nS 5.40nS 5.60nS 5.80nS 6.00nS 6.20nS 6.40nS 6.60nS 6.80nS 7.00nS 7.20nS 7.40nS 7.60nS 7.80nS 8.00nS 8.20nS 8.40nS 8.60nS 8.80nS 9.00nS 9.20nS 9.40nS 9.60nS 9.80nS 10.00nS | [Rising Waveform] R_fixture = 50.00 V_fixture = 3.30 1.00V 1.17V 1.38V 1.57V 1.68V 1.78V 1.91V 2.01V 2.13V 2.22V 2.27V 2.31V 2.35V 2.38V 2.41V 2.43V 2.45V 2.46V 2.48V 2.49V 2.50V 2.51V 2.52V 2.52V 2.53V 2.54V 2.54V 2.55V 2.55V 2.56V 2.56V 2.57V 0.45V 0.54V 0.67V 0.80V 0.88V 0.96V 1.06V 1.15V 1.25V 1.34V 1.40V 1.44V 1.50V 1.56V 1.61V 1.66V 1.70V 1.74V 1.78V 1.82V 1.84V 1.86V 1.88V 1.90V 1.92V 1.93V 1.95V 1.96V 1.97V 1.98V 2.00V 2.00V 1.35V 1.55V 1.80V 2.03V 2.15V 2.26V 2.39V 2.51V 2.61V 2.70V 2.74V 2.77V 2.80V 2.82V 2.84V 2.86V 2.87V 2.88V 2.89V 2.90V 2.91V 2.91V 2.92V 2.92V 2.92V 2.93V 2.93V 2.94V 2.94V 2.94V 2.95V 2.95V V_fixture_min = 3.00 V_fixture_max = 3.60 L_fixture = 0.000H C_fixture = 0.000F | time | 0.000S 0.20nS 0.76V 0.76V 1.03V 1.03V 0.72V 0.72V V(typ) V(min) V(max) Freescale Semiconductor PRELIMINARY 97 Appendix B IBIS Model 0.40nS 0.60nS 0.80nS 1.00nS 1.20nS 1.40nS 1.60nS 1.80nS 2.00nS 2.20nS 2.40nS 2.60nS 2.80nS 3.00nS 3.20nS 3.40nS 3.60nS 3.80nS 4.00nS 4.20nS 4.40nS 4.60nS 4.80nS 5.00nS 5.20nS 5.40nS 5.60nS 5.80nS 6.00nS 6.20nS 6.40nS 6.60nS 6.80nS 7.00nS 7.20nS 7.40nS 7.60nS 7.80nS 8.00nS 8.20nS 8.40nS 8.60nS 8.80nS 9.00nS 0.76V 0.76V 0.77V 0.81V 0.90V 0.98V 1.09V 1.22V 1.35V 1.51V 1.69V 1.91V 2.22V 2.47V 2.65V 2.85V 2.97V 3.08V 3.14V 3.19V 3.23V 3.25V 3.27V 3.28V 3.29V 3.29V 3.30V 3.30V 3.30V 3.30V 3.30V 3.30V 3.30V 3.30V 3.30V 3.30V 3.30V 3.30V 3.30V 3.30V 3.30V 3.30V 3.30V 3.30V 1.03V 1.03V 1.03V 1.03V 1.03V 1.04V 1.11V 1.20V 1.32V 1.45V 1.59V 1.74V 1.96V 2.16V 2.31V 2.49V 2.62V 2.73V 2.83V 2.89V 2.94V 2.95V 2.97V 2.98V 2.99V 2.99V 3.00V 3.00V 3.00V 3.00V 3.00V 3.00V 3.00V 3.00V 3.00V 3.00V 3.00V 3.00V 3.00V 3.00V 3.00V 3.00V 3.00V 3.00V 0.72V 0.72V 0.73V 0.82V 0.93V 1.01V 1.13V 1.26V 1.42V 1.58V 1.78V 2.02V 2.36V 2.63V 2.82V 3.03V 3.17V 3.30V 3.36V 3.42V 3.47V 3.50V 3.52V 3.54V 3.56V 3.57V 3.58V 3.59V 3.59V 3.59V 3.60V 3.60V 3.60V 3.60V 3.60V 3.60V 3.60V 3.60V 3.60V 3.60V 3.60V 3.60V 3.60V 3.60V 98 PRELIMINARY Freescale Semiconductor Appendix B IBIS Model 9.20nS 9.40nS 9.60nS 9.80nS 10.00nS | [Falling Waveform] R_fixture = 50.00 V_fixture = 0.000 3.30V 3.30V 3.30V 3.30V 3.30V 3.00V 3.00V 3.00V 3.00V 3.00V 3.60V 3.60V 3.60V 3.60V 3.60V V_fixture_min = 0.000 V_fixture_max = 0.000 L_fixture = 0.000H C_fixture = 0.000F | time | 0.000S 0.20nS 0.40nS 0.60nS 0.80nS 1.00nS 1.20nS 1.40nS 1.60nS 1.80nS 2.00nS 2.20nS 2.40nS 2.60nS 2.80nS 3.00nS 3.20nS 3.40nS 3.60nS 3.80nS 4.00nS 4.20nS 4.40nS 4.60nS 4.80nS 5.00nS 5.20nS 5.40nS 5.60nS 2.62V 2.62V 2.62V 2.62V 2.60V 2.50V 2.38V 2.29V 2.17V 2.04V 1.89V 1.71V 1.51V 1.27V 0.99V 0.81V 0.71V 0.59V 0.51V 0.44V 0.37V 0.31V 0.26V 0.23V 0.20V 0.17V 0.15V 0.12V 92.71mV 2.12V 2.12V 2.12V 2.12V 2.12V 2.12V 2.11V 2.09V 2.04V 1.96V 1.85V 1.74V 1.63V 1.50V 1.33V 1.17V 1.04V 0.87V 0.72V 0.59V 0.49V 0.40V 0.33V 0.28V 0.25V 0.21V 0.18V 0.14V 0.11V 2.99V 2.99V 2.99V 2.96V 2.85V 2.72V 2.59V 2.50V 2.36V 2.20V 2.00V 1.76V 1.49V 1.23V 0.98V 0.83V 0.75V 0.66V 0.57V 0.50V 0.45V 0.38V 0.32V 0.29V 0.26V 0.23V 0.20V 0.17V 0.14V V(typ) V(min) V(max) Freescale Semiconductor PRELIMINARY 99 Appendix B IBIS Model 5.80nS 6.00nS 6.20nS 6.40nS 6.60nS 6.80nS 7.00nS 7.20nS 7.40nS 7.60nS 7.80nS 8.00nS 8.20nS 8.40nS 8.60nS 8.80nS 9.00nS 9.20nS 9.40nS 9.60nS 9.80nS 10.00nS | 79.46mV 67.17mV 54.74mV 42.77mV 33.26mV 25.46mV 18.21mV 13.43mV 8.06mV 4.81mV 3.27mV 1.98mV 1.32mV 0.78mV 0.50mV 0.42mV 0.34mV 0.30mV 0.27mV 0.24mV 0.21mV 0.22mV 96.17mV 83.01mV 65.86mV 53.06mV 41.31mV 31.29mV 23.99mV 16.92mV 11.32mV 6.46mV 4.82mV 3.62mV 2.10mV 1.45mV 1.01mV 0.70mV 0.61mV 0.51mV 0.45mV 0.40mV 0.35mV 0.32mV 0.12V 0.11V 89.82mV 75.55mV 61.63mV 50.25mV 40.51mV 31.37mV 23.11mV 15.54mV 12.49mV 9.63mV 6.17mV 4.24mV 2.46mV 1.45mV 0.94mV 0.50mV 0.38mV 0.28mV 0.23mV 0.21mV [Falling Waveform] R_fixture = 50.00 V_fixture = 3.30 V_fixture_min = 3.00 V_fixture_max = 3.60 L_fixture = 0.000H C_fixture = 0.000F | time | 0.000S 0.20nS 0.40nS 0.60nS 0.80nS 1.00nS 1.20nS 1.40nS 1.60nS 1.80nS 2.00nS 2.20nS 3.30V 3.30V 3.30V 3.30V 3.30V 3.25V 3.18V 3.14V 3.09V 3.03V 2.96V 2.88V 3.00V 3.00V 3.00V 3.00V 3.00V 3.00V 3.00V 3.00V 3.00V 2.97V 2.92V 2.88V 3.60V 3.60V 3.60V 3.59V 3.52V 3.44V 3.37V 3.32V 3.24V 3.16V 3.07V 2.98V V(typ) V(min) V(max) 100 PRELIMINARY Freescale Semiconductor Appendix B IBIS Model 2.40nS 2.60nS 2.80nS 3.00nS 3.20nS 3.40nS 3.60nS 3.80nS 4.00nS 4.20nS 4.40nS 4.60nS 4.80nS 5.00nS 5.20nS 5.40nS 5.60nS 5.80nS 6.00nS 6.20nS 6.40nS 6.60nS 6.80nS 7.00nS 7.20nS 7.40nS 7.60nS 7.80nS 8.00nS 8.20nS 8.40nS 8.60nS 8.80nS 9.00nS 9.20nS 9.40nS 9.60nS 9.80nS 10.00nS | 2.80V 2.72V 2.61V 2.51V 2.44V 2.34V 2.25V 2.15V 2.06V 1.93V 1.81V 1.73V 1.65V 1.54V 1.44V 1.32V 1.23V 1.18V 1.13V 1.08V 1.04V 1.00V 0.96V 0.93V 0.90V 0.87V 0.85V 0.83V 0.82V 0.81V 0.80V 0.79V 0.78V 0.78V 0.78V 0.77V 0.77V 0.77V 0.77V 2.84V 2.80V 2.74V 2.68V 2.64V 2.58V 2.52V 2.46V 2.39V 2.32V 2.24V 2.20V 2.15V 2.09V 2.04V 1.97V 1.91V 1.87V 1.84V 1.79V 1.75V 1.71V 1.67V 1.63V 1.59V 1.54V 1.48V 1.44V 1.40V 1.35V 1.31V 1.27V 1.23V 1.20V 1.17V 1.15V 1.12V 1.10V 1.09V 2.88V 2.78V 2.65V 2.55V 2.47V 2.35V 2.23V 2.09V 1.93V 1.75V 1.58V 1.50V 1.43V 1.34V 1.26V 1.18V 1.11V 1.07V 1.04V 1.00V 0.96V 0.92V 0.89V 0.87V 0.84V 0.82V 0.80V 0.78V 0.78V 0.76V 0.75V 0.75V 0.74V 0.73V 0.73V 0.73V 0.72V 0.72V 0.72V | End [Model] prd24dgz | |************************************************************************ | Model prt24dgz Freescale Semiconductor PRELIMINARY 101 Appendix B IBIS Model |************************************************************************ | [Model] Model_type Polarity Enable Vmeas = Cref = Rref = Vref = C_comp | | [Temperature Range] [Pullup Reference] [Pulldown Reference] [POWER Clamp Reference] [GND Clamp Reference] [Pulldown] | voltage | -3.30 -3.10 -2.90 -2.70 -2.50 -2.30 -2.10 -1.90 -1.70 -1.50 -1.00 -0.90 -0.80 -0.70 -0.60 -0.50 -0.40 -0.30 -0.20 -0.10 -0.00 0.10 0.20 -10.00mA 0.000A 0.000A 0.000A 0.000A 0.000A -10.00mA -10.00mA -10.00mA -10.00mA -20.00mA -21.00mA -41.70mA -50.60mA -46.07mA -39.45mA -32.03mA -24.30mA -16.36mA -8.26mA 3.97nA 8.11mA 15.76mA 0.000A 0.000A 0.000A 0.000A 0.000A 0.000A 0.000A 0.000A -10.00mA -10.00mA -10.00mA -10.00mA -12.00mA -14.60mA -25.10mA -26.38mA -22.06mA -16.63mA -11.10mA -5.55mA 7.41nA 5.36mA 10.38mA 0.000A -10.00mA 0.000A 0.000A 0.000A -10.00mA -10.00mA -10.00mA -10.00mA -20.00mA -23.00mA -26.00mA -55.37mA -55.11mA -50.21mA -43.90mA -36.09mA -27.49mA -18.57mA -9.40mA 12.45nA 9.30mA 18.18mA I(typ) I(min) I(max) 25.00 3.30V 0.000V 5.00V 0.000V 0.12k 3.00V 0.000V 4.50V 0.000V 0.000 3.60V 0.000V 5.50V 0.000V 1.50V 50.00pF 1.00M 0.000V 4.09pF 3.68pF 4.50pF prt24dgz 3-state Non-Inverting Active-Low 102 PRELIMINARY Freescale Semiconductor Appendix B IBIS Model 0.30 0.40 0.50 0.60 0.70 0.80 0.90 1.00 1.10 1.20 1.30 1.40 1.50 1.60 1.70 1.80 1.90 2.00 2.10 2.20 2.30 2.40 2.50 2.60 2.70 2.80 2.90 3.00 3.10 3.20 3.30 3.40 3.50 3.60 3.70 3.80 3.90 4.00 4.10 4.20 4.30 4.50 4.70 4.90 22.98mA 29.76mA 36.11mA 42.04mA 47.55mA 52.65mA 57.35mA 61.64mA 65.54mA 69.06mA 72.18mA 74.93mA 77.31mA 79.32mA 80.95mA 82.19mA 83.08mA 83.74mA 84.23mA 84.61mA 84.93mA 85.20mA 85.43mA 85.64mA 85.83mA 86.01mA 86.17mA 86.32mA 86.47mA 86.61mA 86.75mA 86.88mA 87.01mA 87.15mA 87.30mA 87.47mA 87.77mA 88.66mA 90.00mA 91.29mA 89.03mA 89.65mA 90.63mA 91.94mA 15.05mA 19.40mA 23.42mA 27.11mA 30.50mA 33.58mA 36.36mA 38.84mA 41.04mA 42.96mA 44.61mA 45.99mA 47.12mA 48.01mA 48.68mA 49.17mA 49.54mA 49.82mA 50.06mA 50.25mA 50.42mA 50.57mA 50.70mA 50.82mA 50.93mA 51.03mA 51.13mA 51.22mA 51.31mA 51.40mA 51.50mA 51.73mA 52.32mA 53.14mA 54.01mA 54.42mA 52.16mA 52.28mA 52.42mA 52.58mA 52.77mA 53.24mA 53.86mA 54.68mA 26.64mA 34.68mA 42.32mA 49.54mA 56.36mA 62.78mA 68.80mA 74.42mA 79.65mA 84.48mA 88.92mA 92.97mA 96.63mA 99.91mA 0.10A 0.11A 0.11A 0.11A 0.11A 0.11A 0.11A 0.11A 0.11A 0.11A 0.11A 0.11A 0.11A 0.11A 0.11A 0.11A 0.11A 0.12A 0.12A 0.12A 0.12A 0.12A 0.12A 0.12A 0.12A 0.12A 0.12A 0.12A 0.12A 0.12A Freescale Semiconductor PRELIMINARY 103 Appendix B IBIS Model 5.10 5.30 5.50 5.70 5.90 6.10 6.60 | [Pullup] | voltage | -3.30 -3.10 -2.90 -2.70 -2.50 -2.30 -2.10 -1.90 -1.70 -1.50 -1.00 -0.90 -0.80 -0.70 -0.60 -0.50 -0.40 -0.30 -0.20 -0.10 0.00 0.10 0.20 0.30 0.40 0.50 0.60 0.70 0.80 0.90 1.00 1.10 1.20 93.62mA 95.73mA 98.29mA 0.10A 0.10A 0.11A 0.12A 55.72mA 57.02mA 58.58mA 60.42mA 62.54mA 64.92mA 71.81mA 0.12A 0.13A 0.13A 0.13A 0.14A 0.14A 0.15A I(typ) 0.22A 0.21A 0.20A 0.19A 0.18A 0.17A 0.16A 0.15A 0.14A 0.12A 92.59mA 84.26mA 75.03mA 65.60mA 56.28mA 47.19mA 37.96mA 28.58mA 19.09mA 9.54mA 0.17uA -9.23mA -17.95mA -26.16mA -33.86mA -41.07mA -47.79mA -54.04mA -59.82mA -65.13mA -69.99mA -74.41mA -78.38mA I(min) 0.16A 0.16A 0.15A 0.14A 0.14A 0.13A 0.12A 0.11A 0.10A 90.13mA 62.48mA 56.95mA 54.36mA 47.69mA 40.63mA 33.52mA 26.49mA 19.70mA 13.03mA 6.45mA 0.16uA -6.17mA -11.99mA -17.46mA -22.57mA -27.35mA -31.77mA -35.86mA -39.62mA -43.05mA -46.15mA -48.92mA -51.38mA I(max) 0.25A 0.24A 0.23A 0.22A 0.21A 0.20A 0.18A 0.17A 0.16A 0.14A 0.11A 97.88mA 87.19mA 76.45mA 66.08mA 55.62mA 44.89mA 33.93mA 22.76mA 11.43mA 0.19uA -11.15mA -21.75mA -31.79mA -41.28mA -50.24mA -58.67mA -66.58mA -73.98mA -80.88mA -87.29mA -93.21mA -98.65mA 104 PRELIMINARY Freescale Semiconductor Appendix B IBIS Model 1.30 1.40 1.50 1.60 1.70 1.80 1.90 2.00 2.10 2.20 2.30 2.40 2.50 2.60 2.70 2.80 2.90 3.00 3.10 3.20 3.30 3.40 3.50 3.60 3.70 3.80 3.90 4.00 4.10 4.20 4.30 4.50 4.70 4.90 5.10 5.30 5.50 5.70 5.90 6.10 6.60 | [GND_clamp] | voltage -81.93mA -85.05mA -87.75mA -90.05mA -91.96mA -93.52mA -94.78mA -95.80mA -96.66mA -97.39mA -98.03mA -98.58mA -99.08mA -99.52mA -99.92mA -0.10A -0.10A -0.10A -0.10A -0.10A -0.10A -0.10A -0.10A -0.10A -0.10A -0.10A -0.11A -0.12A -0.34A -1.90A -3.94A -8.02A -12.10A -16.18A -20.27A -24.35A -28.43A -32.51A -36.60A -40.68A -50.89A -53.52mA -55.36mA -56.88mA -58.12mA -59.09mA -59.84mA -60.43mA -60.92mA -61.35mA -61.72mA -62.06mA -62.37mA -62.65mA -62.91mA -63.15mA -63.37mA -63.58mA -63.78mA -63.96mA -64.14mA -64.33mA -64.95mA -72.61mA -0.17A -0.97A -2.72A -4.50A -6.28A -8.06A -9.85A -11.62A -15.19A -18.75A -22.31A -25.88A -29.44A -33.00A -36.56A -40.13A -43.69A -52.59A -0.10A -0.11A -0.11A -0.12A -0.12A -0.12A -0.12A -0.13A -0.13A -0.13A -0.13A -0.13A -0.13A -0.13A -0.13A -0.13A -0.13A -0.13A -0.14A -0.14A -0.14A -0.14A -0.14A -0.14A -0.14A -0.14A -0.14A -0.14A -0.14A -0.14A -0.15A -1.20A -5.43A -9.67A -13.90A -18.14A -22.38A -26.62A -30.86A -35.09A -45.69A I(typ) I(min) I(max) Freescale Semiconductor PRELIMINARY 105 Appendix B IBIS Model | -3.30 -3.20 -3.10 -3.00 -2.90 -2.80 -2.70 -2.60 -2.50 -2.40 -2.30 -2.20 -2.10 -2.00 -1.90 -1.80 -1.70 -1.60 -1.50 -1.40 -1.30 -1.20 -1.10 -1.00 -0.90 -0.80 -0.70 -0.60 -0.50 -0.40 -0.30 -0.20 -0.10 -0.00 0.10 0.20 0.30 0.40 0.50 0.60 0.70 0.80 0.90 -50.75A -48.72A -46.68A -44.64A -42.60A -40.56A -38.52A -36.48A -34.44A -32.40A -30.36A -28.32A -26.28A -24.24A -22.20A -20.16A -18.12A -16.08A -14.04A -12.00A -9.96A -7.92A -5.88A -3.84A -1.80A -0.23A -13.26mA -2.23mA -0.34mA -28.68uA -1.65uA -0.15uA -86.50nA -76.61nA -68.52nA -60.47nA -52.43nA -44.39nA -36.35nA -28.31nA -20.27nA -12.24nA -4.20nA -47.17A -45.39A -43.61A -41.83A -40.05A -38.27A -36.49A -34.71A -32.93A -31.15A -29.37A -27.59A -25.81A -24.03A -22.25A -20.47A -18.68A -16.90A -15.12A -13.34A -11.56A -9.78A -8.00A -6.22A -4.44A -2.65A -0.90A -0.10A -7.99mA -0.48mA -27.22uA -1.61uA -0.17uA -77.36nA -64.82nA -56.49nA -48.39nA -40.30nA -32.21nA -24.12nA -16.03nA -7.94nA 0.15nA -51.87A -49.75A -47.63A -45.52A -43.40A -41.29A -39.17A -37.05A -34.94A -32.82A -30.70A -28.58A -26.47A -24.35A -22.23A -20.11A -18.00A -15.88A -13.76A -11.64A -9.53A -7.41A -5.29A -3.18A -1.07A -71.53mA -13.93mA -6.08mA -1.62mA -0.18mA -10.18uA -0.42uA -0.11uA -91.73nA -83.30nA -75.01nA -66.73nA -58.46nA -50.19nA -41.93nA -33.68nA -25.42nA -17.17nA 106 PRELIMINARY Freescale Semiconductor Appendix B IBIS Model 1.00 1.10 1.20 1.30 1.40 1.50 1.60 1.70 1.80 1.90 2.00 2.10 2.20 2.30 2.40 2.50 2.60 2.70 2.80 2.90 3.00 3.10 3.20 3.30 | [POWER_clamp] | voltage | -3.30 -3.20 -3.10 -3.00 -2.90 -2.80 -2.70 -2.60 -2.50 -2.40 -2.30 -2.20 -2.10 -2.00 -1.90 -1.80 3.83nA 11.86nA 19.89nA 27.92nA 35.95nA 43.98nA 52.00nA 60.02nA 68.04nA 76.05nA 84.05nA 92.04nA 100.00nA 0.11uA 0.12uA 0.12uA 0.13uA 0.13uA 0.14uA 0.14uA 0.15uA 0.15uA 0.15uA 0.16uA 8.23nA 16.32nA 24.41nA 32.50nA 40.59nA 48.68nA 56.77nA 64.85nA 72.94nA 81.03nA 89.12nA 97.20nA 0.11uA 0.11uA 0.12uA 0.12uA 0.13uA 0.13uA 0.13uA 0.14uA 0.15uA 0.17uA 0.56uA 0.19uA -8.92nA -0.67nA 7.58nA 15.84nA 24.10nA 32.36nA 40.64nA 48.92nA 57.21nA 65.52nA 73.85nA 82.20nA 90.59nA 99.01nA 0.11uA 0.12uA 0.12uA 0.13uA 0.14uA 0.15uA 0.15uA 0.16uA 0.16uA 0.17uA I(typ) 0.37uA 0.37uA 0.36uA 0.35uA 0.35uA 0.34uA 0.33uA 0.33uA 0.32uA 0.32uA 0.31uA 0.30uA 0.30uA 0.29uA 0.28uA 0.28uA I(min) 0.37uA 0.36uA 0.36uA 0.35uA 0.34uA 0.34uA 0.33uA 0.33uA 0.32uA 0.31uA 0.31uA 0.30uA 0.29uA 0.29uA 0.28uA 0.28uA I(max) 0.40uA 0.39uA 0.39uA 0.38uA 0.37uA 0.37uA 0.36uA 0.36uA 0.35uA 0.34uA 0.34uA 0.33uA 0.32uA 0.32uA 0.31uA 0.30uA Freescale Semiconductor PRELIMINARY 107 Appendix B IBIS Model -1.70 -1.60 -1.50 -1.40 -1.30 -1.20 -1.10 -1.00 -0.90 -0.80 -0.70 -0.60 -0.50 -0.40 -0.30 -0.20 -0.10 0.00 | [Ramp] | variable dV/dt_r dV/dt_f R_load = 50.00 | 0.27uA 0.27uA 0.26uA 0.25uA 0.25uA 0.24uA 0.24uA 0.23uA 0.22uA 0.22uA 0.21uA 0.21uA 0.20uA 0.20uA 0.19uA 0.48mA 0.16uA 0.16uA 0.27uA 0.26uA 0.26uA 0.25uA 0.25uA 0.24uA 0.23uA 0.23uA 0.22uA 0.22uA 0.21uA 0.20uA 0.20uA 0.19uA 0.19uA 0.56uA 0.17uA 0.15uA 0.30uA 0.29uA 0.29uA 0.28uA 0.27uA 0.27uA 0.26uA 0.25uA 0.25uA 0.24uA 0.24uA 0.23uA 0.22uA 0.22uA 0.21uA 0.72uA 0.18uA 0.18uA typ 1.54/2.19n 1.52/3.15n min 1.20/2.87n 1.15/4.45n max 1.77/2.14n 1.73/3.01n [Rising Waveform] R_fixture = 50.00 V_fixture = 0.000 V_fixture_min = 0.000 V_fixture_max = 0.000 L_fixture = 0.000H C_fixture = 0.000F | time | 0.000S 0.20nS 0.40nS 0.60nS 0.80nS 1.00nS 1.20nS 1.40nS 1.60nS 0.70uV 0.46uV -5.77uV -0.27mV -2.96mV -3.62mV 19.35mV 46.31mV 79.98mV 0.93uV 0.77uV -1.75uV -5.10uV 26.03uV -5.61uV -0.80mV -3.19mV -6.88mV 0.69uV 0.000V 11.67uV -2.79mV -6.12mV 32.64mV 81.12mV 0.11V 0.16V V(typ) V(min) V(max) 108 PRELIMINARY Freescale Semiconductor Appendix B IBIS Model 1.80nS 2.00nS 2.20nS 2.40nS 2.60nS 2.80nS 3.00nS 3.20nS 3.40nS 3.60nS 3.80nS 4.00nS 4.20nS 4.40nS 4.60nS 4.80nS 5.00nS 5.20nS 5.40nS 5.60nS 5.80nS 6.00nS 6.20nS 6.40nS 6.60nS 6.80nS 7.00nS 7.20nS 7.40nS 7.60nS 7.80nS 8.00nS 8.20nS 8.40nS 8.60nS 8.80nS 9.00nS 9.20nS 9.40nS 9.60nS 9.80nS 10.00nS | [Rising Waveform] 0.12V 0.16V 0.20V 0.26V 0.32V 0.42V 0.51V 0.58V 0.71V 0.85V 1.01V 1.18V 1.38V 1.57V 1.69V 1.79V 1.91V 2.03V 2.14V 2.24V 2.28V 2.31V 2.36V 2.39V 2.41V 2.43V 2.45V 2.46V 2.48V 2.49V 2.50V 2.51V 2.52V 2.52V 2.53V 2.54V 2.54V 2.55V 2.55V 2.56V 2.56V 2.57V -0.22mV 21.89mV 48.68mV 76.62mV 0.11V 0.16V 0.20V 0.24V 0.30V 0.36V 0.45V 0.54V 0.67V 0.81V 0.89V 0.96V 1.06V 1.15V 1.26V 1.35V 1.40V 1.45V 1.51V 1.56V 1.61V 1.66V 1.70V 1.74V 1.78V 1.82V 1.84V 1.86V 1.88V 1.90V 1.92V 1.93V 1.95V 1.96V 1.97V 1.99V 2.00V 2.00V 0.21V 0.27V 0.33V 0.41V 0.49V 0.61V 0.73V 0.82V 0.99V 1.17V 1.36V 1.56V 1.81V 2.03V 2.16V 2.27V 2.40V 2.52V 2.61V 2.70V 2.74V 2.77V 2.80V 2.83V 2.85V 2.86V 2.87V 2.88V 2.89V 2.90V 2.91V 2.91V 2.92V 2.92V 2.93V 2.93V 2.93V 2.94V 2.94V 2.94V 2.95V 2.95V Freescale Semiconductor PRELIMINARY 109 Appendix B IBIS Model R_fixture = 50.00 V_fixture = 3.30 V_fixture_min = 3.00 V_fixture_max = 3.60 L_fixture = 0.000H C_fixture = 0.000F | time | 0.000S 0.20nS 0.40nS 0.60nS 0.80nS 1.00nS 1.20nS 1.40nS 1.60nS 1.80nS 2.00nS 2.20nS 2.40nS 2.60nS 2.80nS 3.00nS 3.20nS 3.40nS 3.60nS 3.80nS 4.00nS 4.20nS 4.40nS 4.60nS 4.80nS 5.00nS 5.20nS 5.40nS 5.60nS 5.80nS 6.00nS 6.20nS 6.40nS 6.60nS 6.80nS 7.00nS 0.76V 0.76V 0.76V 0.76V 0.77V 0.81V 0.90V 0.98V 1.10V 1.22V 1.36V 1.53V 1.72V 1.93V 2.23V 2.48V 2.66V 2.85V 2.97V 3.09V 3.14V 3.19V 3.23V 3.25V 3.27V 3.28V 3.29V 3.29V 3.30V 3.30V 3.30V 3.30V 3.30V 3.30V 3.30V 3.30V 1.03V 1.03V 1.03V 1.03V 1.03V 1.03V 1.03V 1.04V 1.11V 1.21V 1.33V 1.46V 1.60V 1.75V 1.97V 2.16V 2.30V 2.49V 2.63V 2.73V 2.83V 2.89V 2.94V 2.96V 2.97V 2.98V 2.99V 2.99V 3.00V 3.00V 3.00V 3.00V 3.00V 3.00V 3.00V 3.00V 0.72V 0.72V 0.72V 0.72V 0.73V 0.82V 0.93V 1.02V 1.13V 1.26V 1.42V 1.58V 1.80V 2.04V 2.36V 2.62V 2.82V 3.04V 3.19V 3.29V 3.36V 3.42V 3.47V 3.50V 3.52V 3.54V 3.56V 3.57V 3.58V 3.59V 3.59V 3.60V 3.60V 3.60V 3.60V 3.60V V(typ) V(min) V(max) 110 PRELIMINARY Freescale Semiconductor Appendix B IBIS Model 7.20nS 7.40nS 7.60nS 7.80nS 8.00nS 8.20nS 8.40nS 8.60nS 8.80nS 9.00nS 9.20nS 9.40nS 9.60nS 9.80nS 10.00nS | [Falling Waveform] R_fixture = 50.00 V_fixture = 0.000 3.30V 3.30V 3.30V 3.30V 3.30V 3.30V 3.30V 3.30V 3.30V 3.30V 3.30V 3.30V 3.30V 3.30V 3.30V 3.00V 3.00V 3.00V 3.00V 3.00V 3.00V 3.00V 3.00V 3.00V 3.00V 3.00V 3.00V 3.00V 3.00V 3.00V 3.60V 3.60V 3.60V 3.60V 3.60V 3.60V 3.60V 3.60V 3.60V 3.60V 3.60V 3.60V 3.60V 3.60V 3.60V V_fixture_min = 0.000 V_fixture_max = 0.000 L_fixture = 0.000H C_fixture = 0.000F | time | 0.000S 0.20nS 0.40nS 0.60nS 0.80nS 1.00nS 1.20nS 1.40nS 1.60nS 1.80nS 2.00nS 2.20nS 2.40nS 2.60nS 2.80nS 3.00nS 3.20nS 3.40nS 3.60nS 2.62V 2.62V 2.62V 2.62V 2.60V 2.50V 2.37V 2.29V 2.17V 2.04V 1.89V 1.71V 1.50V 1.28V 1.01V 0.82V 0.72V 0.61V 0.51V 2.12V 2.12V 2.12V 2.12V 2.12V 2.12V 2.11V 2.09V 2.04V 1.96V 1.85V 1.74V 1.63V 1.50V 1.33V 1.17V 1.04V 0.87V 0.72V 2.99V 2.99V 2.99V 2.96V 2.85V 2.72V 2.59V 2.50V 2.36V 2.20V 2.00V 1.75V 1.48V 1.24V 1.01V 0.82V 0.75V 0.65V 0.57V V(typ) V(min) V(max) Freescale Semiconductor PRELIMINARY 111 Appendix B IBIS Model 3.80nS 4.00nS 4.20nS 4.40nS 4.60nS 4.80nS 5.00nS 5.20nS 5.40nS 5.60nS 5.80nS 6.00nS 6.20nS 6.40nS 6.60nS 6.80nS 7.00nS 7.20nS 7.40nS 7.60nS 7.80nS 8.00nS 8.20nS 8.40nS 8.60nS 8.80nS 9.00nS 9.20nS 9.40nS 9.60nS 9.80nS 10.00nS | [Falling Waveform] R_fixture = 50.00 V_fixture = 3.30 0.44V 0.38V 0.32V 0.26V 0.23V 0.21V 0.17V 0.15V 0.12V 93.14mV 80.86mV 68.57mV 55.24mV 43.92mV 33.33mV 25.91mV 18.81mV 13.52mV 8.40mV 4.73mV 3.46mV 2.19mV 1.26mV 0.84mV 0.49mV 0.41mV 0.35mV 0.31mV 0.28mV 0.24mV 0.22mV 0.20mV 0.60V 0.49V 0.40V 0.32V 0.28V 0.25V 0.21V 0.18V 0.14V 0.11V 94.78mV 80.67mV 65.96mV 51.39mV 40.71mV 31.19mV 22.83mV 17.13mV 10.61mV 6.73mV 4.67mV 3.16mV 2.23mV 1.32mV 0.95mV 0.74mV 0.58mV 0.51mV 0.45mV 0.40mV 0.36mV 0.32mV 0.50V 0.44V 0.38V 0.32V 0.29V 0.26V 0.23V 0.20V 0.17V 0.14V 0.12V 0.11V 90.13mV 74.96mV 61.03mV 50.31mV 39.65mV 31.61mV 22.62mV 15.75mV 12.43mV 9.14mV 6.37mV 4.12mV 2.29mV 1.55mV 0.81mV 0.53mV 0.39mV 0.27mV 0.24mV 0.21mV V_fixture_min = 3.00 V_fixture_max = 3.60 L_fixture = 0.000H C_fixture = 0.000F | time | 0.000S 0.20nS 3.30V 3.30V 3.00V 3.00V 3.60V 3.60V V(typ) V(min) V(max) 112 PRELIMINARY Freescale Semiconductor Appendix B IBIS Model 0.40nS 0.60nS 0.80nS 1.00nS 1.20nS 1.40nS 1.60nS 1.80nS 2.00nS 2.20nS 2.40nS 2.60nS 2.80nS 3.00nS 3.20nS 3.40nS 3.60nS 3.80nS 4.00nS 4.20nS 4.40nS 4.60nS 4.80nS 5.00nS 5.20nS 5.40nS 5.60nS 5.80nS 6.00nS 6.20nS 6.40nS 6.60nS 6.80nS 7.00nS 7.20nS 7.40nS 7.60nS 7.80nS 8.00nS 8.20nS 8.40nS 8.60nS 8.80nS 9.00nS 3.30V 3.30V 3.30V 3.25V 3.18V 3.14V 3.09V 3.03V 2.96V 2.88V 2.80V 2.72V 2.60V 2.51V 2.44V 2.34V 2.25V 2.15V 2.05V 1.93V 1.81V 1.73V 1.65V 1.53V 1.43V 1.32V 1.22V 1.18V 1.13V 1.08V 1.03V 0.99V 0.96V 0.93V 0.90V 0.87V 0.84V 0.83V 0.82V 0.81V 0.80V 0.79V 0.78V 0.78V 3.00V 3.00V 3.00V 3.00V 3.00V 3.00V 3.00V 2.97V 2.92V 2.88V 2.84V 2.80V 2.74V 2.68V 2.64V 2.58V 2.52V 2.46V 2.39V 2.32V 2.24V 2.19V 2.15V 2.09V 2.04V 1.97V 1.91V 1.87V 1.84V 1.79V 1.75V 1.70V 1.66V 1.63V 1.59V 1.53V 1.47V 1.44V 1.40V 1.35V 1.30V 1.26V 1.23V 1.19V 3.60V 3.59V 3.52V 3.44V 3.37V 3.32V 3.24V 3.16V 3.07V 2.98V 2.88V 2.77V 2.64V 2.54V 2.46V 2.34V 2.22V 2.08V 1.92V 1.74V 1.58V 1.50V 1.42V 1.34V 1.26V 1.18V 1.11V 1.07V 1.03V 0.99V 0.95V 0.92V 0.89V 0.87V 0.84V 0.82V 0.80V 0.78V 0.78V 0.76V 0.75V 0.75V 0.74V 0.73V Freescale Semiconductor PRELIMINARY 113 Appendix B IBIS Model 9.20nS 9.40nS 9.60nS 9.80nS 10.00nS | 0.78V 0.77V 0.77V 0.77V 0.77V 1.17V 1.14V 1.12V 1.10V 1.08V 0.73V 0.73V 0.72V 0.72V 0.72V | End [Model] prt24dgz | |************************************************************************ | | [Model] Model_type Polarity Vinl = Vinh = C_comp | | [Temperature Range] [Pullup Reference] [Pulldown Reference] [POWER Clamp Reference] [GND Clamp Reference] [GND_clamp] | voltage | -5.00 -4.80 -4.60 -4.40 -4.20 -4.00 -3.80 -3.60 -3.40 -3.20 -3.00 -2.80 -2.60 -2.40 -2.20 -2.00 -64.63A -61.55A -58.47A -55.39A -52.31A -49.23A -46.15A -43.07A -39.99A -36.91A -33.82A -30.73A -27.64A -24.56A -21.47A -18.38A -59.13A -56.41A -53.69A -50.97A -48.25A -45.53A -42.81A -40.09A -37.37A -34.65A -31.94A -29.22A -26.51A -23.79A -21.08A -18.36A -66.41A -63.21A -60.01A -56.81A -53.61A -50.41A -47.21A -44.01A -40.81A -37.61A -34.41A -31.22A -28.02A -24.82A -21.62A -18.42A I(typ) I(min) I(max) 25.00 3.30V 0.000V 5.00V 0.000V 0.12k 3.00V 0.000V 4.50V 0.000V 0.000 3.60V 0.000V 5.50V 0.000V 0.000V 3.30V 5.00pF 5.00pF 5.00pF pdusdgz Input Non-Inverting Model pdusdgz |************************************************************************ 114 PRELIMINARY Freescale Semiconductor Appendix B IBIS Model -1.80 -1.60 -1.40 -1.20 -1.00 -0.80 -0.60 -0.40 -0.20 -0.00 0.20 0.40 0.60 0.80 1.00 1.20 1.40 1.60 1.80 2.00 2.20 2.40 2.60 2.80 3.00 3.20 3.40 3.60 3.80 4.00 4.20 4.40 4.60 4.80 5.00 | [POWER_clamp] | voltage | -5.00 -4.90 -4.80 -4.70 -4.60 -15.29A -12.20A -9.12A -6.03A -2.94A -0.20A -1.85mA -83.24uA -60.52uA -60.40uA -60.32uA -60.23uA -60.11uA -59.96uA -59.74uA -59.32uA -58.35uA -56.47uA -53.57uA -49.55uA -43.70uA -3.73uA 0.10uA 0.12uA 0.13uA 0.14uA 0.15uA 0.16uA 0.17uA 0.18uA 0.18uA 0.19uA 0.20uA 0.21uA 0.22uA -15.64A -12.93A -10.21A -7.50A -4.78A -2.07A -96.40mA -0.50mA -36.82uA -35.33uA -35.27uA -35.20uA -35.13uA -35.03uA -34.91uA -34.50uA -33.59uA -31.92uA -29.25uA -7.60uA -16.78nA 0.10uA 0.11uA 0.12uA 0.13uA 0.20uA 0.15uA 96.30nA 43.50nA -9.30nA -62.10nA -0.11uA -0.17uA -0.22uA -0.27uA -15.22A -12.03A -8.83A -5.63A -2.43A -64.17mA -4.85mA -0.23mA -86.29uA -85.95uA -85.85uA -85.73uA -85.57uA -85.37uA -85.08uA -84.56uA -83.44uA -81.36uA -78.20uA -73.89uA -68.43uA -61.70uA -51.99uA -2.43uA 0.13uA 0.14uA 0.15uA 0.16uA 0.17uA 0.18uA 0.19uA 0.20uA 0.21uA 0.22uA 0.23uA I(typ) 0.61uA 0.60uA 0.59uA 0.59uA 0.58uA I(min) 0.59uA 0.58uA 0.58uA 0.57uA 0.56uA I(max) 0.65uA 0.65uA 0.64uA 0.63uA 0.63uA Freescale Semiconductor PRELIMINARY 115 Appendix B IBIS Model -4.50 -4.40 -4.30 -4.20 -4.10 -4.00 -3.90 -3.80 -3.70 -3.60 -3.50 -3.40 -3.30 -3.20 -3.10 -3.00 -2.90 -2.80 -2.70 -2.60 -2.50 -2.40 -2.30 -2.20 -2.10 -2.00 -1.90 -1.80 -1.70 -1.60 -1.50 -1.40 -1.30 -1.20 -1.10 -1.00 -0.90 -0.80 -0.70 -0.60 -0.50 -0.40 -0.30 -0.20 0.57uA 0.56uA 0.56uA 0.55uA 0.54uA 0.54uA 0.53uA 0.52uA 0.52uA 0.51uA 0.50uA 0.50uA 0.49uA 0.48uA 0.48uA 0.47uA 0.46uA 0.46uA 0.45uA 0.44uA 0.44uA 0.43uA 0.42uA 0.42uA 0.41uA 0.40uA 0.39uA 0.39uA 0.38uA 0.37uA 0.37uA 0.36uA 0.35uA 0.35uA 0.34uA 0.33uA 0.33uA 0.32uA 0.31uA 0.31uA 0.30uA 0.29uA 0.29uA 0.28uA 0.56uA 0.55uA 0.54uA 0.54uA 0.53uA 0.52uA 0.52uA 0.51uA 0.50uA 0.50uA 0.49uA 0.48uA 0.48uA 0.47uA 0.46uA 0.46uA 0.45uA 0.44uA 0.44uA 0.43uA 0.42uA 0.41uA 0.41uA 0.40uA 0.39uA 0.39uA 0.38uA 0.37uA 0.37uA 0.36uA 0.35uA 0.35uA 0.34uA 0.33uA 0.33uA 0.32uA 0.31uA 0.31uA 0.30uA 0.29uA 0.29uA 0.28uA 0.27uA 0.27uA 0.62uA 0.61uA 0.60uA 0.60uA 0.59uA 0.58uA 0.58uA 0.57uA 0.56uA 0.56uA 0.55uA 0.54uA 0.53uA 0.53uA 0.52uA 0.51uA 0.51uA 0.50uA 0.49uA 0.49uA 0.48uA 0.47uA 0.46uA 0.46uA 0.45uA 0.44uA 0.44uA 0.43uA 0.42uA 0.42uA 0.41uA 0.40uA 0.39uA 0.39uA 0.38uA 0.37uA 0.37uA 0.36uA 0.35uA 0.35uA 0.34uA 0.33uA 0.32uA 0.32uA 116 PRELIMINARY Freescale Semiconductor Appendix B IBIS Model -0.10 0.00 | 0.27uA 0.27uA 0.26uA 0.25uA 0.31uA 0.30uA | End [Model] pdusdgz | |************************************************************************ | | [Model] Model_type Polarity Vinl = Vinh = C_comp | | [Temperature Range] [Pullup Reference] [Pulldown Reference] [POWER Clamp Reference] [GND Clamp Reference] [GND_clamp] | voltage | -5.00 -4.80 -4.60 -4.40 -4.20 -4.00 -3.80 -3.60 -3.40 -3.20 -3.00 -2.80 -2.60 -2.40 -2.20 -2.00 -1.80 -1.60 -1.40 -64.63A -61.55A -58.47A -55.39A -52.31A -49.23A -46.15A -43.07A -39.99A -36.91A -33.82A -30.73A -27.64A -24.56A -21.47A -18.38A -15.29A -12.20A -9.12A -59.13A -56.41A -53.69A -50.97A -48.25A -45.53A -42.81A -40.09A -37.37A -34.65A -31.94A -29.22A -26.51A -23.79A -21.08A -18.36A -15.64A -12.93A -10.21A -66.41A -63.21A -60.01A -56.81A -53.61A -50.41A -47.21A -44.01A -40.81A -37.61A -34.41A -31.22A -28.02A -24.82A -21.62A -18.42A -15.22A -12.03A -8.83A I(typ) I(min) I(max) 25.00 3.30V 0.000V 5.00V 0.000V 0.12k 3.00V 0.000V 4.50V 0.000V 0.000 3.60V 0.000V 5.50V 0.000V 0.000V 3.30V 5.00pF 5.00pF 5.00pF pdddgz Input Non-Inverting Model pdddgz |************************************************************************ Freescale Semiconductor PRELIMINARY 117 Appendix B IBIS Model -1.20 -1.00 -0.80 -0.60 -0.40 -0.20 -0.00 0.20 0.40 0.60 0.80 1.00 1.20 1.40 1.60 1.80 2.00 2.20 2.40 2.60 2.80 3.00 3.20 3.40 3.60 3.80 4.00 4.20 4.40 4.60 4.80 5.00 | [POWER_clamp] | voltage | -5.00 -4.90 -4.80 -4.70 -4.60 -4.50 -4.40 -4.30 -6.03A -2.94A -0.20A -1.89mA -85.69uA -27.91uA -87.50nA 18.71uA 29.18uA 32.49uA 33.06uA 33.29uA 33.44uA 33.56uA 33.66uA 33.76uA 33.85uA 33.94uA 33.99uA 34.01uA 34.02uA 34.03uA 34.04uA 34.06uA 34.08uA 34.10uA 34.12uA 34.14uA 34.16uA 34.18uA 34.20uA 34.22uA -7.50A -4.78A -2.07A -96.41mA -0.50mA -14.61uA -88.83nA 7.31uA 10.24uA 10.66uA 10.78uA 10.85uA 10.91uA 10.96uA 11.01uA 11.06uA 11.10uA 11.12uA 11.13uA 11.14uA 11.15uA 11.16uA 11.25uA 11.17uA 11.09uA 11.01uA 10.93uA 10.85uA 10.77uA 10.69uA 10.61uA 10.53uA -5.63A -2.43A -64.21mA -4.91mA -0.24mA -42.88uA -0.10uA 32.27uA 54.12uA 65.78uA 69.33uA 70.16uA 70.54uA 70.78uA 70.98uA 71.15uA 71.30uA 71.44uA 71.59uA 71.74uA 71.82uA 71.84uA 71.85uA 71.87uA 71.89uA 71.91uA 71.93uA 71.95uA 71.97uA 71.99uA 72.01uA 72.03uA I(typ) 48.19uA 47.87uA 47.55uA 47.23uA 46.91uA 46.59uA 46.27uA 45.95uA I(min) 16.29uA 16.17uA 16.05uA 15.93uA 15.81uA 15.69uA 15.57uA 15.45uA I(max) 95.53uA 95.03uA 94.53uA 94.03uA 93.53uA 93.03uA 92.53uA 92.03uA 118 PRELIMINARY Freescale Semiconductor Appendix B IBIS Model -4.20 -4.10 -4.00 -3.90 -3.80 -3.70 -3.60 -3.50 -3.40 -3.30 -3.20 -3.10 -3.00 -2.90 -2.80 -2.70 -2.60 -2.50 -2.40 -2.30 -2.20 -2.10 -2.00 -1.90 -1.80 -1.70 -1.60 -1.50 -1.40 -1.30 -1.20 -1.10 -1.00 -0.90 -0.80 -0.70 -0.60 -0.50 -0.40 -0.30 -0.20 -0.10 0.00 | 45.63uA 45.31uA 44.99uA 44.67uA 44.35uA 44.03uA 43.71uA 43.39uA 43.07uA 42.75uA 42.43uA 42.11uA 41.79uA 41.47uA 41.15uA 40.83uA 40.51uA 40.19uA 39.87uA 39.55uA 39.23uA 38.91uA 38.59uA 38.27uA 37.95uA 37.63uA 37.31uA 36.99uA 36.68uA 36.38uA 36.11uA 35.86uA 35.63uA 35.41uA 35.22uA 35.05uA 34.90uA 34.77uA 34.65uA 34.55uA 34.47uA 34.40uA 34.34uA 15.33uA 15.21uA 15.09uA 14.97uA 14.85uA 14.73uA 14.61uA 14.49uA 14.37uA 14.25uA 14.13uA 14.01uA 13.89uA 13.77uA 13.65uA 13.53uA 13.41uA 13.29uA 13.17uA 13.05uA 12.93uA 12.81uA 12.69uA 12.57uA 12.45uA 12.33uA 12.22uA 12.11uA 12.01uA 11.92uA 11.84uA 11.76uA 11.69uA 11.63uA 11.57uA 11.52uA 11.48uA 11.44uA 11.41uA 11.38uA 11.35uA 11.33uA 11.31uA 91.53uA 91.03uA 90.53uA 90.03uA 89.53uA 89.03uA 88.53uA 88.03uA 87.53uA 87.03uA 86.53uA 86.03uA 85.53uA 85.03uA 84.53uA 84.03uA 83.53uA 83.03uA 82.53uA 82.03uA 81.53uA 81.03uA 80.53uA 80.03uA 79.53uA 79.03uA 78.53uA 78.03uA 77.53uA 77.03uA 76.53uA 76.03uA 75.53uA 75.06uA 74.63uA 74.24uA 73.89uA 73.58uA 73.30uA 73.06uA 72.86uA 72.68uA 72.54uA Freescale Semiconductor PRELIMINARY 119 Appendix B IBIS Model | End [Model] pdddgz | |************************************************************************ | | [Model] Model_type Polarity Vinl = Vinh = C_comp | | [Temperature Range] [Pullup Reference] [Pulldown Reference] [POWER Clamp Reference] [GND Clamp Reference] [GND_clamp] | voltage | -5.00 -4.80 -4.60 -4.40 -4.20 -4.00 -3.80 -3.60 -3.40 -3.20 -3.00 -2.80 -2.60 -2.40 -2.20 -2.00 -1.80 -1.60 -1.40 -1.20 -1.00 -0.80 -64.63A -61.55A -58.47A -55.39A -52.31A -49.23A -46.15A -43.07A -39.99A -36.91A -33.82A -30.73A -27.64A -24.56A -21.47A -18.38A -15.29A -12.20A -9.12A -6.03A -2.94A -0.20A -59.13A -56.41A -53.69A -50.97A -48.25A -45.53A -42.81A -40.09A -37.37A -34.65A -31.94A -29.22A -26.51A -23.79A -21.08A -18.36A -15.64A -12.93A -10.21A -7.50A -4.78A -2.07A -66.41A -63.21A -60.01A -56.81A -53.61A -50.41A -47.21A -44.01A -40.81A -37.61A -34.41A -31.22A -28.02A -24.82A -21.62A -18.42A -15.22A -12.03A -8.83A -5.63A -2.43A -64.17mA I(typ) I(min) I(max) 25.00 3.30V 0.000V 5.00V 0.000V 0.12k 3.00V 0.000V 4.50V 0.000V 0.000 3.60V 0.000V 5.50V 0.000V 0.000V 3.30V 5.00pF 5.00pF 5.00pF pdudgz Input Non-Inverting Model pdudgz |************************************************************************ 120 PRELIMINARY Freescale Semiconductor Appendix B IBIS Model -0.60 -0.40 -0.20 -0.00 0.20 0.40 0.60 0.80 1.00 1.20 1.40 1.60 1.80 2.00 2.20 2.40 2.60 2.80 3.00 3.20 3.40 3.60 3.80 4.00 4.20 4.40 4.60 4.80 5.00 | [POWER_clamp] | voltage | -5.00 -4.90 -4.80 -4.70 -4.60 -4.50 -4.40 -4.30 -4.20 -4.10 -4.00 -1.85mA -83.24uA -60.52uA -60.40uA -60.32uA -60.23uA -60.11uA -59.96uA -59.74uA -59.32uA -58.35uA -56.47uA -53.57uA -49.55uA -43.70uA -3.73uA 0.10uA 0.12uA 0.13uA 0.14uA 0.15uA 0.16uA 0.17uA 0.18uA 0.18uA 0.19uA 0.20uA 0.21uA 0.22uA -96.40mA -0.50mA -36.82uA -35.33uA -35.27uA -35.20uA -35.13uA -35.03uA -34.87uA -34.50uA -33.59uA -31.92uA -29.25uA -7.60uA -16.78nA 0.10uA 0.11uA 0.12uA 0.13uA 0.20uA 0.15uA 96.30nA 43.50nA -9.30nA -62.10nA -0.11uA -0.17uA -0.22uA -0.27uA -4.85mA -0.23mA -86.29uA -85.95uA -85.85uA -85.73uA -85.57uA -85.37uA -85.08uA -84.56uA -83.44uA -81.36uA -78.20uA -73.89uA -68.43uA -61.70uA -51.99uA -2.43uA 0.13uA 0.14uA 0.15uA 0.16uA 0.17uA 0.18uA 0.19uA 0.20uA 0.21uA 0.22uA 0.23uA I(typ) 0.61uA 0.60uA 0.59uA 0.59uA 0.58uA 0.57uA 0.56uA 0.56uA 0.55uA 0.54uA 0.54uA I(min) 0.59uA 0.58uA 0.58uA 0.57uA 0.56uA 0.56uA 0.55uA 0.54uA 0.54uA 0.53uA 0.52uA I(max) 0.65uA 0.65uA 0.64uA 0.63uA 0.63uA 0.62uA 0.61uA 0.60uA 0.60uA 0.59uA 0.58uA Freescale Semiconductor PRELIMINARY 121 Appendix B IBIS Model -3.90 -3.80 -3.70 -3.60 -3.50 -3.40 -3.30 -3.20 -3.10 -3.00 -2.90 -2.80 -2.70 -2.60 -2.50 -2.40 -2.30 -2.20 -2.10 -2.00 -1.90 -1.80 -1.70 -1.60 -1.50 -1.40 -1.30 -1.20 -1.10 -1.00 -0.90 -0.80 -0.70 -0.60 -0.50 -0.40 -0.30 -0.20 -0.10 0.00 | 0.53uA 0.52uA 0.52uA 0.51uA 0.50uA 0.50uA 0.49uA 0.48uA 0.48uA 0.47uA 0.46uA 0.46uA 0.45uA 0.44uA 0.44uA 0.43uA 0.42uA 0.42uA 0.41uA 0.40uA 0.39uA 0.39uA 0.38uA 0.37uA 0.37uA 0.36uA 0.35uA 0.35uA 0.34uA 0.33uA 0.33uA 0.32uA 0.31uA 0.31uA 0.30uA 0.29uA 0.29uA 0.28uA 0.27uA 0.27uA 0.52uA 0.51uA 0.50uA 0.50uA 0.49uA 0.48uA 0.48uA 0.47uA 0.46uA 0.46uA 0.45uA 0.44uA 0.44uA 0.43uA 0.42uA 0.41uA 0.41uA 0.40uA 0.39uA 0.39uA 0.38uA 0.37uA 0.37uA 0.36uA 0.35uA 0.35uA 0.34uA 0.33uA 0.33uA 0.32uA 0.31uA 0.31uA 0.30uA 0.29uA 0.29uA 0.28uA 0.27uA 0.27uA 0.26uA 0.25uA 0.58uA 0.57uA 0.56uA 0.56uA 0.55uA 0.54uA 0.53uA 0.53uA 0.52uA 0.51uA 0.51uA 0.50uA 0.49uA 0.49uA 0.48uA 0.47uA 0.46uA 0.46uA 0.45uA 0.44uA 0.44uA 0.43uA 0.42uA 0.42uA 0.41uA 0.40uA 0.39uA 0.39uA 0.38uA 0.37uA 0.37uA 0.36uA 0.35uA 0.35uA 0.34uA 0.33uA 0.32uA 0.32uA 0.31uA 0.30uA | End [Model] pdudgz | |************************************************************************ 122 PRELIMINARY Freescale Semiconductor Appendix B IBIS Model | | [Model] Model_type Polarity Vinl = Vinh = C_comp | | [Temperature Range] [Pullup Reference] [Pulldown Reference] [POWER Clamp Reference] [GND Clamp Reference] [GND_clamp] | voltage | -5.00 -4.80 -4.60 -4.40 -4.20 -4.00 -3.80 -3.60 -3.40 -3.20 -3.00 -2.80 -2.60 -2.40 -2.20 -2.00 -1.80 -1.60 -1.40 -1.20 -1.00 -0.80 -0.60 -0.40 -0.20 -64.63A -61.55A -58.47A -55.39A -52.31A -49.23A -46.15A -43.07A -39.99A -36.91A -33.82A -30.73A -27.64A -24.56A -21.47A -18.38A -15.29A -12.20A -9.12A -6.03A -2.94A -0.20A -1.79mA -22.83uA -0.15uA I(typ) 25.00 3.30V 0.000V 3.30V 5.00pF pdidgz Input Non-Inverting Model pdidgz |************************************************************************ 5.00pF 5.00pF 0.12k 3.00V 0.000V 4.50V 0.000V I(min) -59.13A -56.41A -53.69A -50.97A -48.25A -45.53A -42.81A -40.09A -37.37A -34.65A -31.94A -29.22A -26.51A -23.79A -21.08A -18.36A -15.64A -12.93A -10.21A -7.50A -4.78A -2.07A -96.39mA -0.47mA -1.56uA I(max) -66.41A -63.21A -60.01A -56.81A -53.61A -50.41A -47.21A -44.01A -40.81A -37.61A -34.41A -31.22A -28.02A -24.82A -21.62A -18.42A -15.22A -12.03A -8.83A -5.63A -2.43A -64.14mA -4.77mA -0.14mA -0.37uA 0.000 3.60V 0.000V 5.50V 0.000V 0.000V 5.00V 0.000V Freescale Semiconductor PRELIMINARY 123 Appendix B IBIS Model -0.00 0.20 0.40 0.60 0.80 1.00 1.20 1.40 1.60 1.80 2.00 2.20 2.40 2.60 2.80 3.00 3.20 3.40 3.60 3.80 4.00 4.20 4.40 4.60 4.80 5.00 | [POWER_clamp] | voltage | -5.00 -4.90 -4.80 -4.70 -4.60 -4.50 -4.40 -4.30 -4.20 -4.10 -4.00 -3.90 -3.80 -3.70 -88.71nA -72.38nA -56.11nA -39.84nA -23.57nA -7.31nA 8.94nA 25.19nA 41.42nA 57.64nA 73.83nA 89.95nA 0.11uA 0.12uA 0.13uA 0.14uA 0.15uA 0.15uA 0.16uA 0.17uA 0.18uA 0.19uA 0.20uA 0.20uA 0.21uA 0.22uA -89.34nA -68.50nA -52.12nA -35.76nA -19.40nA -3.04nA 13.32nA 29.68nA 46.03nA 62.39nA 78.74nA 94.86nA 0.11uA 0.12uA 0.13uA 0.14uA 0.21uA 0.15uA 0.10uA 47.20nA -5.80nA -58.80nA -0.11uA -0.16uA -0.22uA -0.27uA -0.11uA -88.30nA -71.55nA -54.82nA -38.12nA -21.42nA -4.73nA 11.97nA 28.68nA 45.42nA 62.20nA 79.06nA 96.02nA 0.11uA 0.13uA 0.14uA 0.15uA 0.16uA 0.17uA 0.18uA 0.18uA 0.19uA 0.20uA 0.21uA 0.22uA 0.23uA I(typ) 0.60uA 0.60uA 0.59uA 0.58uA 0.58uA 0.57uA 0.56uA 0.56uA 0.55uA 0.54uA 0.54uA 0.53uA 0.52uA 0.52uA I(min) 0.59uA 0.58uA 0.58uA 0.57uA 0.56uA 0.56uA 0.55uA 0.54uA 0.54uA 0.53uA 0.52uA 0.52uA 0.51uA 0.50uA I(max) 0.65uA 0.64uA 0.64uA 0.63uA 0.62uA 0.62uA 0.61uA 0.60uA 0.59uA 0.59uA 0.58uA 0.57uA 0.57uA 0.56uA 124 PRELIMINARY Freescale Semiconductor Appendix B IBIS Model -3.60 -3.50 -3.40 -3.30 -3.20 -3.10 -3.00 -2.90 -2.80 -2.70 -2.60 -2.50 -2.40 -2.30 -2.20 -2.10 -2.00 -1.90 -1.80 -1.70 -1.60 -1.50 -1.40 -1.30 -1.20 -1.10 -1.00 -0.90 -0.80 -0.70 -0.60 -0.50 -0.40 -0.30 -0.20 -0.10 0.00 | | End [Model] pdidgz 0.51uA 0.50uA 0.49uA 0.49uA 0.48uA 0.47uA 0.47uA 0.46uA 0.45uA 0.45uA 0.44uA 0.43uA 0.43uA 0.42uA 0.41uA 0.41uA 0.40uA 0.39uA 0.39uA 0.38uA 0.37uA 0.37uA 0.36uA 0.35uA 0.35uA 0.34uA 0.33uA 0.33uA 0.32uA 0.31uA 0.31uA 0.30uA 0.29uA 0.29uA 0.28uA 0.28uA 0.27uA 0.50uA 0.49uA 0.48uA 0.48uA 0.47uA 0.46uA 0.46uA 0.45uA 0.44uA 0.43uA 0.43uA 0.42uA 0.41uA 0.41uA 0.40uA 0.39uA 0.39uA 0.38uA 0.37uA 0.37uA 0.36uA 0.35uA 0.35uA 0.34uA 0.33uA 0.33uA 0.32uA 0.31uA 0.31uA 0.30uA 0.29uA 0.29uA 0.28uA 0.27uA 0.27uA 0.26uA 0.26uA 0.55uA 0.55uA 0.54uA 0.53uA 0.53uA 0.52uA 0.51uA 0.51uA 0.50uA 0.49uA 0.48uA 0.48uA 0.47uA 0.46uA 0.46uA 0.45uA 0.44uA 0.44uA 0.43uA 0.42uA 0.42uA 0.41uA 0.40uA 0.39uA 0.39uA 0.38uA 0.37uA 0.37uA 0.36uA 0.35uA 0.35uA 0.34uA 0.33uA 0.33uA 0.32uA 0.31uA 0.31uA Freescale Semiconductor PRELIMINARY 125 Appendix B IBIS Model Revision History Revision 0.0 Date 27 April 2004 Initial release Description 126 PRELIMINARY Freescale Semiconductor NOTES How to Reach Us: Home Page: www.freescale.com USA/Europe or Locations Not Listed: Freescale Semiconductor Technical Information Center, CH370 1300 N. Alma School Road Chandler, Arizona 85224 1-800-521-6274 or 480-768-2130 Europe, Middle East, and Africa: Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen, Germany +44 1296 380 456 (English) +46 8 52200080 (English) +49 89 92103 559 (German) +33 1 69 35 48 48 (French) Japan: Freescale Semiconductor Japan Ltd. Headquarters ARCO Tower 15F 1-8-1, Shimo-Meguro, Meguro-ku Tokyo 153-0063 Japan 0120 191014 or +81 3 5437 9125 support-japan@freescale.com Asia/Pacific: Freescale Semiconductor Hong Kong Ltd. Technical Information Center 2 Dai King Street Tai Po Industrial Estate Tai Po, N.T., Hong Kong 852-26668334 For Literature Requests Only: Freescale Semiconductor Literature Distribution Center P.O. Box 5405 Denver, Colorado 80217 1-800-441-2447 or 303-675-2140 Fax: 303-675-2150 Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. Freescale Semiconductor reserves the right to make changes without further notice to any products herein. Freescale Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters that may be provided in Freescale Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals", must be validated for each customer application by customer's technical experts. Freescale Semiconductor does not convey any license under its patent rights nor the rights of others. Freescale Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold Freescale Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part. FreescaleTM and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. (c) Freescale Semiconductor, Inc. 2004. All rights reserved. DSP56374 Rev. 1 11/2004 |
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